Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a capacitor device within a recessed portion of a substrate. The recessed portion has sidewalls and a bottom surface below a top surface of the substrate. The semiconductor structure includes a dielectric material disposed below the capacitor device and within the recessed portion. The semiconductor structure includes a first conductive structure adjacent one or more of the sidewalls of the recessed portion. The first conductive structure may include a conductive portion of the substrate or a conductive material disposed within the recessed portion. The semiconductor structure includes a second conductive structure coupled to the first conductive structure, where the second conductive structure provides an electrical connection from the first conductive structure to a voltage source or a voltage drain.

The present disclosure provides a semiconductor package structure, relating to the technical field of semiconductors. The semiconductor package structure includes: a substrate; and at least one chip stack structure provided on the substrate, where the at least one chip stack structures include a plurality of first chips vertically stacked, each of the first chips includes a first conductive plug set, a connection layer is provided between two adjacent first chips, a wire structure is provided in the connection layer, the wire structure is electrically connected to the first conductive plug sets in two first chips adjacent to the wire structure, projections of two first conductive plug sets electrically connected to a same wire structure on the substrate are staggered from each other, and the first conductive plug sets in the plurality of first chips are connected in series through the wire structures to form an inductor structure.

A semiconductor chip includes a lower wiring layer, a multilayer wiring layer formed on the lower wiring layer, and an upper wiring layer formed on the multilayer wiring layer. Here, a thickness of a wiring provided in the lower wiring layer is larger than a thickness of each of a plurality of wirings provided in the multilayer wiring layer, and a thickness of a wiring provided in the upper wiring layer is larger than the thickness of each of the plurality of wirings provided in the multilayer wiring layer. A lower inductor which is a component of a transformer is provided in the lower wiring layer, and an upper inductor which is a component of the transformer is provided in the upper wiring layer.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode that includes a bottom region and a pair of vertical regions. First metal layers are outside the vertical regions and in contact with the vertical regions. An insulator is over the first electrode. A second electrode is over the insulator. A second metal layer is on a top surface of the second electrode.

A semiconductor package and a method for forming the same are provided. The method includes: providing a substrate; mounting a semiconductor die on a top surface of the substrate; forming a barrier wall on a peripheral area of a top surface of the semiconductor die; dispensing a first fluid material on the top surface of the semiconductor die, wherein the barrier wall prevents the first fluid material from flowing across it; and curing the first fluid material to form a back side metallization (BSM) layer.

A semiconductor device includes a semiconductor fin, a gate structure, a capacitor structure, a conductive contact, a hard mask layer, and a pair of spacers. The gate structure is disposed across the semiconductor fin. The capacitor structure is disposed on and in physical contact with the gate structure. The conductive contact is disposed on and in physical contact with the capacitor structure. The conductive contact is a single-layered structure. The hard mask layer laterally surrounds the conductive contact. The spacers laterally surround the gate structure and the hard mask layer. A top surface of the hard mask layer is levelled with top surfaces of the spacers, and the conductive contact extends from below the top surfaces of the spacers to above the top surfaces of the spacers.

A method for making a three dimensional (3D) Metal-Insulator-Metal (MIM) capacitor and trenches by etching a dielectric layer to form a via or contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via or contact hole, the tub, and the trench, wherein the deposited conformal metal forms bottom and sidewall portions of a 3D bottom electrode of a metal-insulator-metal (MIM) capacitor in the tub, and wherein the deposited conformal metal forms a via or contact in the via or contact hole; removing conformal metal and at least a portion of the dielectric layer from a lip of the tub; depositing an insulator layer on the 3D bottom electrode to form an insulator layer of the MIM capacitor; and depositing a metal layer on the insulator layer to form a top electrode of the MIM capacitor.

A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.