A contact with low contact resistance is provided in the present invention, including a dielectric layer on a substrate, a contact hole formed in the dielectric layer and exposing the substrate, an N-type or P-type metal oxide film on the surface of contact hole, a barrier layer on the metal oxide film, and a contact plug on the barrier layer and filling up the contact hole, wherein a 2DEG or 2DHG is formed in the substrate near the contact surface between the contact and the substrate.

A semiconductor device, a manufacturing method, and an electronic device capable of achieving both formation of a capacitive element and reduction in parasitic capacitance. A semiconductor device includes an internal electrode on a first surface side of a semiconductor substrate, a through hole at a position corresponding to the internal electrode, a first rewiring on a second surface side of the semiconductor substrate and connected to the internal electrode via the through hole, a second rewiring connected to the first rewiring on a side closer to an external connection terminal than the first rewiring, and an interlayer insulating film between the first and second rewirings. Two of a first internal electrode and a second internal electrode are provided as the internal electrode, and the first rewiring connected to the first internal electrode, the second rewiring connected to the second internal electrode, and the interlayer insulating film constitute a capacitor.

An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.

A method of making a semiconductor structure includes defining a first recess in an insulation layer. The method further includes forming a protection layer along a sidewall of the first recess. The method further includes forming a first conductive line in the first recess and in direct contact with the protection layer. The method further includes depositing a first insulation material over the first conductive line. The method further includes defining a second recess in the first insulation material. The method further includes forming a second conductive line in the second recess. The method further includes forming a via extending from the second conductive line, wherein the via directly contacts a sidewall of the protection layer.

A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.

There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.

Interconnect structures having dielectric layers with nitrogen-containing crusts and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a first interconnect opening in a first interlayer dielectric (ILD) layer that exposes an underlying conductive feature, such as a source/drain, a gate, a contact, a via, or a conductive line. The method includes nitridizing sidewalls of the first interconnect opening, which are formed by the first ILD layer, before forming a first metal contact in the first interconnect opening. The nitridizing converts a portion of the first ILD layer into a nitrogen-containing crust. The first metal contact can include a metal plug and dielectric spacers between the metal plug and the nitrogen-containing crust of the first ILD layer. The method can include forming a second interconnect opening in a second ILD layer that exposes the first metal contact and forming a second metal contact in the second interconnect opening.

The present disclosure is directed to conductive structures that may be utilized in a radio-frequency (RF) switch. The embodiments of the conductive structures of the present disclosure are formed to balance the on resistance (R.sub.on) and the off capacitance (C.sub.off) such that the R.sub.on.Math.C.sub.off value is optimized such that the conductive structures are relatively efficient as compared to conventional conductive structures within conventional RF switches. For example, the conductive structures include various metallization layers that are stacked on each other and spaced apart in a selected manner to balance the R.sub.on and the C.sub.off as to optimize the R.sub.on.Math.C.sub.off figure of merit as a lower R.sub.on.Math.C.sub.off is preferred.

The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature, and a contact via structure. The conductive feature is over the substrate. The contact via structure is electrically coupled to the conductive feature and includes a curved concave profile throughout a height of the contact via structure and an upper width wider than the width of the conductive feature.

The embodiments herein relate to contact via structures of semiconductor devices and methods of forming the same. A semiconductor device is provided. The semiconductor device includes a substrate, a conductive feature, and a contact via structure. The conductive feature is over the substrate. The contact via structure is electrically coupled to the conductive feature and includes a curved concave profile throughout a height of the contact via structure and an upper width wider than the width of the conductive feature.