A method for manufacturing a semiconductor structure includes: forming a device portion and a front interconnect portion on a base substrate; forming a first bonding part on the front interconnect portion opposite to the device portion, the first bonding part including a first bonding layer and heat-dissipating elements formed in the first bonding layer, a thermal resistance of the heat-dissipating elements being smaller than a thermal resistance of the first bonding layer; forming a second bonding part on a carrier substrate; and performing a bonding process to bond the second bonding part to the first bonding part.

An integrated electronic device includes at least one component produced on a carrier structure including a semiconductor substrate, and an interconnection track (8) that runs over the carrier structure from the component to a lateral face of the device. The interconnection track includes a layer of oxidizable material bearing a continuous layer of conductive material. The layer of oxidizable material is discontinuous. A method for producing such an integrated electronic device is also disclosed herein.

Metal-insulator-metal (MIM) capacitor, an integrated semiconductor device having a MIM capacitor and methods of making. The MIM capacitor includes a first metal layer, a second metal layer and a dielectric layer located between the second metal layer and the first metal layer. The first metal layer, the second metal layer and the dielectric layer may be formed in a comb structure, wherein the comb structure include a first tine structure and at least a second tine structure.

A semiconductor structure is provided. The semiconductor structure includes a first die and a second die. The first die includes a substrate, an interconnection structure and a capacitor structure. The substrate has a front-side surface and a back-side surface. The interconnection structure is disposed over the front-side surface. The capacitor structure extends from the back-side surface to the front-side surface and into the interconnection structure. The second die is disposed over the back-side surface and is bonded to the first die. A method for forming a semiconductor structure is also provided.

A semiconductor device including a transistor on a substrate; an interlayer insulating layer on the transistor; a first metal-containing layer on the interlayer insulating layer; and a second metal-containing layer on the first metal-containing layer, wherein the second metal-containing layer includes a resistor, the resistor includes a first insulating layer on the first metal-containing layer; a resistor metal layer on the first insulating layer, and a second insulating layer on the resistor metal layer, and the resistor metal layer includes a recessed side surface.

A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device, where the MIM capacitor surrounds a first Mx metal line. A semiconductor device including a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device, where the MIM capacitor surrounds a first Mx metal line, where a lower horizontal surface of the MIM capacitor is vertically adjacent to an upper horizontal surface of an Mx-1 metal line. A method including forming a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device, where the MIM capacitor surrounds a first Mx metal line.

A package substrate according to an embodiment includes a first substrate; and a first chip mounted on the first substrate; wherein the first substrate includes: a first insulating layer including a first region overlapping the first chip in a vertical direction and a second region other than the first region; and a circuit pattern disposed on the first region and the second region of the first insulating layer; wherein the circuit pattern includes: a pad portion including a first portion disposed on an upper surface of the second region of the first insulating layer, a second portion buried in the first region of the first insulating layer, and a third portion including at least a part buried in the first region of the first insulating layer and connecting between the first portion and the second portion; wherein at least a part of the first chip is disposed in the first region of the first insulating layer; wherein the first region of the first insulating layer surrounds a lower surface and a side surface of the first chip, and wherein the first region and the second region of the first insulating layer are a single insulating layer.

A package substrate according to an embodiment includes a first substrate; and a first chip mounted on the first substrate; wherein the first substrate includes: a first insulating layer including a first region overlapping the first chip in a vertical direction and a second region other than the first region; and a circuit pattern disposed on the first region and the second region of the first insulating layer; wherein the circuit pattern includes: a pad portion including a first portion disposed on an upper surface of the second region of the first insulating layer, a second portion buried in the first region of the first insulating layer, and a third portion including at least a part buried in the first region of the first insulating layer and connecting between the first portion and the second portion; wherein at least a part of the first chip is disposed in the first region of the first insulating layer; wherein the first region of the first insulating layer surrounds a lower surface and a side surface of the first chip, and wherein the first region and the second region of the first insulating layer are a single insulating layer.

An integrated circuit package and the method of forming the same are provided. The integrated circuit package may include an integrated circuit die and a dielectric material on sidewalls of the integrated circuit die. The integrated circuit die may include a substrate, a protective structure in the substrate, an interconnect structure on the substrate, and a seal ring structure in the interconnect structure and in contact with the protective structure. The protective structure and the substrate may include a same semiconductor material, and the protective structure may include a first dopant and a second dopant different from the first dopant. The interconnect structure may include dielectric layers and conductive features in the dielectric layers. The seal ring structure may encircle the conductive features of the interconnect structure in a top-down view.

A semiconductor package includes a package substrate, a bridge chip structure including a plurality of bridge chips that are accommodated in the package substrate and stacked in a vertical direction, and a plurality of semiconductor chips that are arranged on the package substrate and are electrically connected to each other through the bridge chip structure, wherein each of the plurality of bridge chips has different sizes.