A method for depositing an oxide film on a substrate by a cyclical deposition is disclosed. The method may include: depositing a metal oxide film over the substrate utilizing at least one deposition cycle of a first sub-cycle of the cyclical deposition process; and depositing a silicon oxide film directly on the metal oxide film utilizing at least one deposition cycle of a second sub-cycle of the cyclical deposition process. Semiconductor device structures including an oxide film deposited by the methods of the disclosure are also disclosed.

Methods for selective deposition are provided. Material is selectively deposited on a first surface of a substrate relative to a second surface of a different material composition. An inhibitor, such as a polyimide layer, is selectively formed from vapor phase reactants on the first surface relative to the second surface. A layer of interest is selectively deposited from vapor phase reactants on the second surface relative to the first surface. The first surface can be metallic while the second surface is dielectric. Accordingly, material, such as a dielectric transition metal oxides and nitrides, can be selectively deposited on metallic surfaces relative dielectric surfaces using techniques described herein.

A method for producing a ferroelectric layer or antiferroelectric layer in which a layer of a paraelectric material already deposited on a surface of a substrate with a layer thickness of at least two crystallographic unit cells is introduced into an alternating electric field. The alternating electric field is repeatedly cycled between a positive electric field strength and a negative electric field strength of amplitude greater than the coercivity field strength of the material such that the layer of paraelectric material forms a polarization.

A method for fabricating a semiconductor device includes: forming a first oxide layer containing a first element over a first electrode layer; forming a second oxide layer containing a second element over the first oxide layer; forming a stacked structure in which a plurality of first oxide layers and a plurality of second oxide layers are alternately stacked by repeating the forming of the first oxide layer and the forming of the second oxide layer a plurality of times; and forming a second electrode layer over the stacked structure, wherein a thickness of a lowermost first oxide layer among the plurality of first oxide layers is greater than a thickness of each of other first oxide layers.

A method for depositing protective layers on a surface of a substrate includes conducting a plurality of ALD cycles in a first reaction chamber to deposit a first protective layer on the substrate. Each ALD cycle of the plurality of ALD cycles is conducted at a deposition temperature below about 100 C. and includes delivering a first precursor gas into the first reaction chamber containing the substrate. A reacting portion of the first precursor gas is absorbed onto a surface of the substrate to form a first sub-layer of the protective layer. A second precursor gas is delivered into the first reaction chamber containing the substrate, a reacting portion of the second precursor gas being absorbed onto the surface of the substrate to form a second sub-layer of the protective layer. Metrology analysis is performed on the substrate within a second reaction chamber.

In an embodiment, a method for nitriding a substrate is provided. The method includes flowing a nitrogen-containing source and a carrier gas into a plasma processing source coupled to a chamber such that a flow rate of the nitrogen-containing source is from about 3% to 20% of a flow rate of the carrier gas; generating an inductively-coupled plasma (ICP) in the plasma processing source by operating an ICP source, the ICP comprising a radical species formed from the nitrogen-containing source, the carrier gas, or both; and nitriding the substrate within the chamber, wherein nitriding includes operating a heat source within the chamber at a temperature from about 150 C. to about 650 C. to heat the substrate; maintaining a pressure of the chamber from about 50 mTorr to about 2 Torr; introducing the ICP to the chamber; and adjusting a characteristic of the substrate by exposing the substrate to the radical species.

A semimetal liner and a metal-insulator-metal (MIM) capacitor (MIMCAP) are described along with the methods of manufacture or fabrication. The MIM capacitor structure includes a liner formed of a thin layer or film of a semimetal, which is a few nanometers thick, e.g., a thickness in the range of about 0.5 nm to about 5 nm or more. The semimetal liner is sandwiched between an electrode layer and a dielectric layer, e.g., a layer of high or ultra-high-k material, thereby providing a cap for the electrode to limit leakage currents in the structure.

An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

The present disclosure relates to methods and apparatuses for selective deposition on a surface. In particular, a silicon-containing inhibitor can be used to selectively bind to a first region, thus inhibiting deposition of a material on that first region.

Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high- dielectric layer on the interfacial layer, a dipole layer on the high- dielectric layer, and a capping layer on the dipole layer. In some embodiments, the dipole layer comprises a metal oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-k dielectric layer.