A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

A method for forming a semiconductor device structure is provided. The method includes forming a first conductive structure surrounded by a first dielectric layer and forming a second dielectric layer over the first conductive structure and the first dielectric layer. The method also includes forming a via hole in the second dielectric layer, and the via hole exposes the first conductive structure. The method further includes partially removing the first conductive structure through the via hole to form a recess in the first conductive structure. In addition, the method includes forming a second conductive structure filling the recess and the via hole.

Methods of forming an integrated circuit devices may include providing first and second active regions, an isolation layer, and first and second sacrificial stack structures. The first and second sacrificial stack structures may contact the first and second active regions, and the first and second sacrificial stack structures may each include a channel layer and a sacrificial layer. The methods may also include forming an etch stop layer on the isolation layer, replacing portions of the first and second sacrificial stack structures with first and second source/drain regions, forming a front contact including a front contact plug, forming a back-side insulator, and forming a back contact plug in the isolation layer and the back-side insulator. At least one of a portion of the front contact plug and a portion of the back contact plug may be in the etch stop layer.

Embodiments of the present disclosure provide methods of forming a RDL structure with a flat passivation surface. Some embodiments provide a stop layer for chemical mechanical polishing disposed under a passivation layer. Some embodiments provide an extra thickness of passivation deposition and a sacrificial passivation layer for passivation polishing. Some embodiments provide a modified RDL pattern by inserting dummy pattern objects to adjust pattern density.

A layer of conductive material is formed above a bottom-most layer of interconnect structures in an interconnect layer of a semiconductor device, and the layer of conductive material is etched to define the bottom-most layer of metallization structures from the layer of conductive material. To reduce the likelihood of collapse of the free-standing metallization structures, the exposed sidewall surfaces of the free-standing metallization structures may be oxidized to form metal-oxide sidewalls for the free-standing metallization structures. The metal-oxide sidewalls may be formed using a self-aligned oxidation technique that specifically targets the sidewalls of the free-standing metallization structures for oxidation. The metal-oxide sidewalls may be formed of a metal-oxide material that increases the mechanical strength of the free-standing metallization structures, which enables the free-standing metallization structures to resist collapsing.

There is provided a process of forming a film containing a metal element, an additional element different from the metal element and at least one of nitrogen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a first precursor gas containing the metal element and a second precursor gas containing the additional element to the substrate so that supply periods of the first precursor gas and the second precursor gas at least partially overlap with each other; and (b) supplying a reaction gas containing the at least one of nitrogen and carbon to the substrate.

The present disclosure provides a semiconductor structure and a method for manufacturing the same. The semiconductor structure at least includes: an underlying conductive layer and a blocking portion, a plane in which the blocking portion is located being located above a plane in which the underlying conductive layer is located, and projections of the blocking portion and the underlying conductive layer in the vertical direction having an overlapping region; a three-dimensional structure, the three-dimensional structure including a first portion and a second portion, a top surface of the blocking portion being higher than a bottom surface of the second portion and being lower than or flush with a bottom surface of the first portion, and at least a part of the first portion being located directly above the overlapping region; a contact hole and a first conductive layer, a plane in which the first conductive layer is located being higher than a top surface of the three-dimensional structure, the contact hole being directly connected to the first conductive layer, the underlying conductive layer being electrically connected to the first conductive layer through the contact hole, and the contact hole being located on a side of the first portion away from the second portion; and a first isolation layer, the first isolation layer being configured to fill a region between the contact hole and the three-dimensional structure and a region between different contact holes.

An integrated chip includes a first metal line disposed over a substrate. A via is disposed directly over a top of the first metal line and the via has a first lower surface and a second lower surface above the first lower surface. A first dielectric structure is disposed laterally adjacent to the first metal line and along a sidewall of the first metal line. A first protective etch-stop structure is disposed directly over a top of the first dielectric structure and vertically separates the second lower surface of the via from the top of the first dielectric structure.

A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.