A method and corresponding device structure includes depositing a metal fill material on at least one electrical connection formed in a feature formed within a first dielectric layer of a semiconductor device structure, wherein the metal fill material completely fills the feature. The method further includes depositing a protective layer over an upper surface of the metal fill material, and depositing a barrier layer over the protective layer.

A semiconductor device may include a first active pattern and a second active pattern on a substrate, a device isolation layer in a trench between the first active pattern and the second active pattern, a first channel pattern and a second channel pattern provided on the first active pattern and the second active pattern, respectively, each of the first channel pattern and the second channel pattern including a plurality of stacked semiconductor patterns, and a gate electrode on the first channel pattern and the second channel pattern. The device isolation layer may include a first portion and a second portion which are vertically overlapped with the gate electrode. The first portion may be provided on the second portion. A silicon concentration of the first portion may be higher than a silicon concentration of the second portion.