A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a first component, a second component, and a protective element. The first component and the second component are arranged side by side in a first direction over the carrier. The protective element is disposed over a top surface of the carrier and extending from space under the first component toward a space under the second component. The protective element includes a first portion and a second portion protruded oppositely from edges of the first component by different distances, and the first portion and the second portion are arranged in a second direction angled with the first direction.

A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip via a second bonding material. The first semiconductor chip includes: a protective film; and a first pad electrode exposed from the protective film in a first opening portion of the protective film. The second semiconductor chip is mounted on the first pad electrode of the first semiconductor chip via the second bonding material. The second bonding material includes: a first member being in contact with the first pad electrode; and a second member interposed between the first member and the second semiconductor chip. The first member is a conductive bonding material of a film shape, and the second member is an insulating bonding material of a film shape.

A lead frame according to the present embodiments includes: a main body portion having a main surface including a mounting region on which a semiconductor chip is to be mounted; a lead portion connected to the main body portion; a groove portion provided in a main surface of the main body portion so as to surround the mounting region, the groove portion having an inner side surface and an outer side surface; and a protruding portion protrudingly provided along an inner edge of the groove portion.

A semiconductor device includes: a substrate; an adhesive member arranged on a surface of the substrate; a first chip stacked on the adhesive member with a first adhesive piece interposed therebetween; and a second chip stacked on the first chip with a second adhesive piece interposed therebetween. The adhesive member has a multilayer structure including a pair of surface layers formed of a cured product of a thermosetting resin composition and an intermediate layer arranged between the pair of surface layers.

In one example, a semiconductor device includes a conductive structure having a conductive structure upper side. A roughening is on the conductive structure upper side and a groove is in the conductive structure extending partially into the conductive structure from the conductive structure upper side. An electronic component is attached to the conductive structure upper side with an attachment film. An encapsulant covers the electronic component, at least portions of the roughening, and at least portions of the conductive structure upper side. The groove has smoothed sidewalls that include substantially planarized portions of the roughening. The smooth sidewalls reduce flow of the attachment film across the conductive structure upper side to improve adhesion of the encapsulant to the conductive structure. Other examples and related methods are also disclosed herein.

Provided is a switching device 1 including a drain fin 103 arranged below a semiconductor chip 101 via a common mode current suppression structure 2. The common mode current suppression structure 2 includes a first insulating layer 2a joined on the drain fin 103, an electric conductive layer 2b joined on the first insulating layer 12a, a second insulating layer 2c joined on the electric conductive layer 2b, and an electrode conductor 2d joined on an upper surface of the second insulating layer 2c and joined to a drain electrode 101a of the semiconductor chip 101. The electric conductive layer 2b is electrically connected to a source electrode 101b of the semiconductor chip 101.

A device comprises a substrate) of a first material with a surface, which is modified by depositing a bi-layer nanoparticle film. The film includes a nanoparticle layer of a second material on top of and in contact with surface, and a nanoparticle layer of a third material on top of and in contact with the nanoparticle layer of the second material. The nanoparticles of the third material adhere to the nanoparticles of the second material. The substrate region adjoining surface comprises an admixture of the second material in the first material. A fourth material contacts and chemically/mechanically bonds to the nanoparticle layer of the third material.

A semiconductor device includes: a first terminal and a second terminal; a first conductive member that is electrically connected to the first terminal; a semiconductor chip that is provided on the first conductive member; a second conductive member that is provided on the semiconductor chip and electrically connected to the second terminal; a first insulator that is provided on the second conductive member and covers the semiconductor chip; a conductive plate that is provided on at least a part of the first insulator; and a post that is electrically connected to the conductive plate and extends along a side surface of the first insulator.

A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising an encapsulant, the first layer being arranged on the substrate and covering the first metallization layer the at least one semiconductor body, wherein the first layer is configured to release liquid or oil at temperatures exceeding a defined threshold temperature.

In one example, an electronic device, comprises a substrate comprising a dielectric structure and a conductive structure, an electronic component over a top side of the substrate, wherein the electronic component is coupled with the conductive structure; an encapsulant over the top side of the substrate and contacting a lateral side of the electronic component, wherein the encapsulant comprises a first trench on a top side of the encapsulant adjacent to the electronic component, a lid over the top side of the encapsulant and covering the electronic component; and an interface material between the top side of the encapsulant and the lid, and in the first trench. Other examples and related methods are also disclosed herein.