A semiconductor device is provided, which is configured to improve the adhesion between the resin part and the leads without interfering with proper operation of the semiconductor device. The semiconductor device includes a semiconductor element 1, a first lead 2 including a first pad portion 21, a second lead 3 including a second pad portion 31, a conductor member 61, and a resin part 8. The first pad portion 21 has a first-pad obverse surface 21a including a first smooth region 211 to which an element reverse surface 1b is bonded, and a first rough region 212 spaced apart from the semiconductor element 1 as viewed in z direction and has a higher roughness than the first smooth region 211. The second pad portion 31 has a second-pad obverse surface 31a including a second smooth region 311 to which a second bonding portion 612 is bonded, and a second rough region 312 spaced apart from the second bonding portion 612 as viewed in z direction and has a higher roughness than the second smooth region 311.

A power semiconductor device includes a semiconductor structure comprising an active region, an encapsulation material on the semiconductor structure, and a plurality of adhesion features in or on the semiconductor structure along an interface with the encapsulation material. The interface is laterally between the active region and at least one edge of the semiconductor structure. Related devices and fabrication methods are also discussed.

A semiconductor device includes a heat sink, a base material including an insulating layer and mounted on the heat sink on one side in a first direction, a first conductive layer bonded to the base material and located on a side opposite the heat sink with respect to the base material, a first semiconductor element bonded to the first conductive layer, a first power terminal electrically connected to the first conductive layer and the first semiconductor element, and a sealing resin covering the first conductive layer and the first semiconductor element. The first power terminal is exposed from the sealing resin. The first power terminal is surrounded by a peripheral edge of the sealing resin as viewed in the first direction.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

A semiconductor package includes a first redistribution structure including a plurality of first redistribution layers and a plurality of first redistribution vias. A semiconductor chip is on the first redistribution structure. The semiconductor chip includes a chip pad. A connection pad is between the first redistribution structure and the semiconductor chip, and is connected to the first redistribution structure. A connection bump is connected to the connection pad and the chip pad. A molding layer extends around the first redistribution structure and the semiconductor chip, and a through electrode extends through the molding layer. A wetting layer is between the first redistribution structure and the molding layer.

An electronic device is provided. An example electronic device includes: a semiconductor body of Silicon Carbide, having a surface having a first portion of the surface that defines an active region of the electronic device and a second portion of the surface that is external to the active region; a metallization extending on the first portion of the surface of the semiconductor body; a passivation layer extending on part of the metallization; and an adhesion layer, based on one or more carbon allotropes, extending on the passivation layer.

A sensor package includes a circuit substrate, a sensor die, an electrical connection, a dielectric dam, a cover layer, and an encapsulant. The circuit substrate includes a first side, a second side opposite to the first side, and a cavity recessed from the first side toward the second side. The sensor die is disposed in the cavity and includes a first side, a sensing area on the first side, and a second side opposite to the first side and facing the circuit substrate. The electrical connection electrically connects the first sides of the sensor die and the circuit substrate. The dielectric dam is disposed on the first side of the circuit substrate and outside the cavity, and the dielectric dam partially covers the electrical connection. The encapsulant is disposed on the first side of the circuit substrate and laterally covers the dielectric dam and the cover layer.

A semiconductor package includes a connector connected to a semiconductor chip; a first redistribution layer including a first redistribution pattern; a second redistribution layer including a second redistribution pattern; and an under-bump metallization (UBM) pad disposed on the second redistribution layer; the second redistribution pattern including a redistribution pad aligned with the UBM pad and a side surface extending beyond a side surface of the UBM pad in a first direction; the first redistribution pattern including first redistribution lines comprising a first line aligned with a first edge of the redistribution pad and a second line aligned with a second edge of the redistribution pad; a first side surface of the first line extending farther in the first direction than the first edge of the redistribution pad, and a first side surface of the second line extending farther in the first direction than the second edge of the redistribution pad.

Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.