Design and construction of high interconnection density, minimal loss I/O channels comprising embedded passive networks that preserve signal integrity at signaling frequencies above 1 GHz, preferably above 10 GHz, to improve memory-processor bandwidths.

According to an example aspect of the present invention, there is provided a wafer-level package (1), comprising a top substrate (10) and a bottom substrate (30), wherein the top substrate (10) comprises a recess (12) on a side of the top substrate (10) which is towards the bottom substrate (30) and the bottom substrate (30) comprises a recess (32) on a side of the bottom substrate (30) which is towards the top substrate (10), wherein the recess (12) of the top substrate (10) and the recess (32) of the bottom substrate (30) are arranged to form a waveguide (5) within the wafer-level package (1) and a middle substrate (20) arranged to couple an integrated circuit (24) of the wafer-level package (1) to the waveguide (5), wherein the middle substrate (20) is in between the top substrate (10) and the bottom substrate (30) and the middle substrate (20) comprises a probe (21), wherein the probe (21) extends to the waveguide (5) and the probe (21) is arranged to couple a signal coming from the integrated circuit (24) to the waveguide (5), or to couple a signal coming from the waveguide (5) to the integrated circuit (24).

A semiconductor device includes a first die having ports and a second die having ports. The semiconductor device includes a multi-layer package substrate. The multi-layer package substrate includes a first layer patterned to include pads for the ports of the first die and the second die and a second layer patterned to provide vias between the pads for the ports of the first die and pads for the ports of the second die and a third layer of the multi-layer package substrate. The third layer is patterned to provide traces that couple the vias coupled to ports of the first die to vias coupled to ports of the second die to couple the first die to the second die, the traces of the third layer having a width. The multi-layer package substrate also includes a fourth layer underlying the third layer and a ground plane underlying the fourth layer.

A laminate substrate for an RF application includes: a first metal layer in which is formed a first slot and a transmission line penetrating into the first slot; a second metal layer comprising a second laterally closed slot; a third metal layer comprising a third laterally closed slot; a fourth metal layer comprising a fourth slot; a dielectric layer being arranged between each metal layer; the second slot, the third slot, and the fourth slot forming a vertical RF feedthrough in the substrate; at least one of the third metal layer or the fourth metal layer having a portion protruding, respectively, into the third slot or into the fourth slot.

A radio frequency (RF) device includes at least one RF chip, including a local oscillator configured to generate an RF signal. The RF device further includes an RF signal path coupling an output of the at least one RF chip and an input of the at least one RF chip, wherein the RF signal path is configured to feed the generated RF signal from the output of the at least one RF chip into the input of the at least one RF chip. The RF device further includes a processing unit coupled to the input of the at least one RF chip and configured to perform in a first mode at least one of testing, monitoring or calibrating the at least one RF chip based on the generated RF signal.

One example includes a method for fabricating a substrate-integrated waveguide (SIW). The method includes forming a first metal layer on a carrier surface. The first metal layer can extend along an axis. The method also includes forming a first metal sidewall extending from a first edge of the first metal layer along the axis and forming a second metal sidewall extending from a second edge of the first metal layer opposite the first edge along the axis to form a trough extending along the axis. The method also includes providing a dielectric material over the first metal layer and over the first and second metal sidewalls. The method further includes forming a second metal layer over the dielectric material and over the first and second metal sidewalls. The second metal layer can extend along the axis to enclose the SIW in all radial directions along the axis.

A tunable coupler for making a controllable coupling to at least a first qubit is disclosed. The tunable coupler includes a first constant coupling element and a tunable coupling element. The first constant coupling element forms a non-galvanic coupling interface to at least the first qubit at a first extremity that is distant from the tunable coupling element. The tunable coupling element is located adjacent to a non-galvanic coupling interface formed as an interface to a circuit element at a second extremity thereof.

Embodiments of the subject disclosure are directed to, for example, a circuit or device that includes a package corresponding to a first waveguide, a die corresponding to a second waveguide, and an array of bump balls disposed between the package and the die. Various embodiments may include a circuit or device that includes a plurality of ground planes, a plurality of ground bump balls, and a plurality of package ground planes, where the plurality of ground planes, the plurality of ground bump balls, and the plurality of package ground planes form a Faraday cage. Other embodiments are disclosed.