A semiconductor wafer comprising a first die including a first integrated circuit having a trimmable or programmable component. The trimmable or programmable component is configured to be trimmed or permanently altered in response to an electrical signal. The semiconductor wafer also includes a saw street arranged adjacent to the first die, and at least one probe pad electrically connected to the trimmable or programmable component. The at least one probe pad is arranged in the saw street.

A memory device includes a memory cell having a transistor and a resistor coupled to each other, where the memory cell is on the first side, and the transistor further includes a plurality of first sub-transistors disposed in a first region of the substate. The memory device includes a plurality of second sub-transistors disposed in a second region of the substrate. The memory device further includes a first interconnect structure disposed on the second side. The first sub-transistors are each coupled to the first interconnect structure through a plurality of first via structures. The second sub-transistors are each coupled to the first interconnect structure through a plurality of second via structures and at least a third via structure, where the first via structures and the second via structures each have a first cross-sectional area, and the third via structure has a second cross-sectional area that is different from the first cross-sectional area.

A capacitor module includes a first die and a second die. Each of the first die and the second die includes a capacitor device and a circuit structure electrically connected to the capacitor device. The circuit structure includes a pad and a first signal line. The first signal line includes a first pad connection portion and a first signal transmission portion. The first pad connection portion is located below the pad and is electrically connected to the pad. The first signal transmission portion is electrically connected to the capacitor device. The first signal line of the first die further includes first fuses connecting the first pad connection portion and the first signal transmission portion. The first signal line of the second die is broken, so that the first pad connection portion of the second die is electrically separated from the first signal transmission portion.

A semiconductor device structure and a method of manufacturing the same are provided. The semiconductor device structure includes a substrate, a fuse structure, and a first word line. The fuse structure includes a fuse electrode disposed within the substrate. The first word line is electrically coupled to the fuse structure. The first word line is disposed within the substrate and spaced apart from the fuse electrode of the fuse structure. The fuse electrode has a lateral surface protruding toward the first word line.

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a fuse metal, a doped structure, a first dielectric layer, a second dielectric layer and two doped portions. The first dielectric layer extends along a first direction and disposed above the fuse metal. The first dielectric layer includes a first recess structure for accommodating the fuse metal. The doped structure is formed above the first dielectric layer and extends along a second direction vertical to the first direction. The second dielectric layer extends along the first direction and is disposed above the doped structure. The doped portions are adjacent to two lateral surfaces of the doped structure, and the doped portions are spaced apart from the first dielectric layer and the second dielectric layer.

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a lower supporting frame; an upper supporting frame, and a capacitor component. The lower supporting frame is disposed over the substrate. The upper supporting frame is disposed over and spaced apart from the lower supporting frame. The capacitor component is disposed over the substrate. The capacitor component includes a lower electrode having a noncontinuous sidewall abutting the lower supporting frame.

Back-end-of-line (BEOL) interconnect fuses are described. In an example, an integrated circuit structure includes a first dielectric layer having first conductive lines therein. A second dielectric layer is over the first dielectric layer and has first conductive vias and second conductive lines therein. One of the second conductive lines is a fuse element. A third dielectric layer is over the second dielectric layer and has second conductive vias and third conductive lines therein. The second dielectric layer has a lower dielectric constant than the first dielectric layer and than the third dielectric layer, or the second dielectric layer has a lower thermal conductivity than the first dielectric layer and than the third dielectric layer, or both.

An electric fuse element has a first portion, a second portion arranged on one end of the first portion, and a third portion arranged on the other end of the first portion. A resistor element is arranged separately from the electric fuse element. A material of each of the electric fuse element and the resistor element has silicon metal or nickel chromium. The electric fuse element and the resistor element are arranged in an upper layer of the first wiring and in lower layer of the second wiring. A wiring width of the second portion and a wiring width of the third portion are larger than a wiring width of the first portion.

Structures for an electronic fuse and methods of forming an electronic fuse. The structure comprises an electronic fuse including a first terminal, a second terminal, and a fuse link extending from the first terminal to the second terminal. The first terminal, the second terminal, and the fuse link each include a semiconductor layer and a silicide layer. The silicide layer includes a first portion on the first terminal, a second portion on the second terminal, and a third portion on the fuse link. The fuse link includes an airgap between the semiconductor layer and the third portion of the silicide layer.

A method and an electronic device that includes an isolation structure having a dielectric material on or in a semiconductor surface layer, and a passive circuit component having a metal silicide structure on a side of the isolation structure, there the metal silicide structure includes a metal silicide portion and a dielectric portion, the dielectric portion of the metal silicide structure including one of silicon nitride, silicon oxide, silicon carbide, silicon carbon nitride, and silicon oxynitride. The method includes forming a dielectric material of the isolation structure on or in the semiconductor surface layer, forming a silicon-rich dielectric layer on a side of the isolation structure, and siliciding the silicon-rich dielectric layer to form the metal silicide structure on the side of the isolation structure.