The present application provides a metal gate structure of a high-voltage device and a method for making the same, forming a dummy gate on the gate oxide layer, wherein the dummy gate is composed of a plurality of polysilicon structures spaced apart from each other; forming a protective layer on sidewalls of the plurality of polysilicon structures and on the gate oxide layer between the polysilicon structures; performing covering with an insulating layer to fill a region between the polysilicon structures, wherein the filled region forms an insulating structure; removing the polysilicon structure to form a groove; forming a metal layer, wherein the metal layer covers the insulating structure and fills the groove; and polishing the surface of the metal layer, wherein the insulating structure, the protective layer, and the metal layer form a metal gate with a planarized surface.

A method of fabricating a semiconductor device, including forming first and second active patterns on a substrate, in which the first and second active patterns are spaced apart, forming gate electrodes on the first and second active patterns, in which the gate electrodes are spaced apart, and forming a non-linear gate separation structure between the first and second active patterns, including a first side facing the second active pattern, and a second side opposite to the first side, a distance from the second active pattern to the first side of a first portion of the non-linear gate separation structure is smaller than a distance to the first side of a second portion of the non-linear gate separation structure, and a distance from the second active pattern to the second side of the first portion is smaller than a distance to the second side of the second portion.

A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.

Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

A chip scale semiconductor package comprises a silicon layer, a back side metal layer, and a plurality of front side pads. Each of the plurality of front side pads comprises a respective copper member and a respective solder member. A method comprises the steps of: providing a wafer; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process.

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first set of nanostructures and a second set of nanostructures on the substrate, a first gate electrode wrapping the first set of nanostructures and the second set of nanostructures, and a gate-cut structure between the first set of nanostructures and the second set of nanostructures. The gate-cut structure includes a barrier layer adjacent to the first gate electrode and a dielectric layer spaced apart from the first gate electrode by the barrier layer.

A semiconductor structure includes a substrate with fin features extending along a first direction; a plurality of gate stacks and a plurality of dummy pillars. The gate stacks are deposited over the substrate and extend along a second direction different from the first direction to cover the sidewalls and top surfaces of the fin features exposed from the substrate. Each gate stack includes a first gate region, a second gate region and a central region formed between the first gate region and the second gate region without covering the fin features. The dummy pillars are formed in the gate stacks besides the fin features and/or on the fin features.

A method of manufacturing an integrated circuit device includes forming a plurality of nanosheet stacked structures on a substrate; forming a gate cut hole; forming a gate cut structure filling the gate cut hole; sequentially forming a substrate insulating layer and a lower wiring structure on the gate cut structure, a plurality of gate spacers, and a lower surface of a plurality of fin-type active areas; and forming an upper wiring structure on an interlayer insulating layer.

A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.