A semiconductor package includes: a base chip; semiconductor chips disposed on the base chip and including front pads disposed on a front surface opposing the base chip, rear pads disposed on a rear surface opposing the front surface, and through-vias; bumps disposed between the semiconductor chips; a dam structure disposed on at least a portion of the rear pads; and insulating adhesive layers at least partially surrounding the bumps and the dam structure, wherein the rear pads include first pads that are disposed in a center region that crosses a center of the rear surface and that are electrically connected to the through-vias, and second pads that are disposed in a peripheral region adjacent to the center region, wherein the second pads include a line pad of which at least a portion has a polygonal shape, and wherein the dam structure has a bent shape.

A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

A semiconductor device includes: a lower semiconductor structure including a plurality of first lower electrode bonding pads, a plurality of second lower electrode bonding pads, and a lower connection pattern connecting the plurality of first lower electrode bonding pads to each other while being connected to a first voltage; and an upper semiconductor structure disposed over the lower semiconductor structure and including a plurality of first upper electrode bonding pads, a plurality of second upper electrode bonding pads, and an upper connection pattern connecting the plurality of second upper electrode bonding pads to each other while being connected to a second voltage different from the first voltage, wherein the plurality of first lower electrode bonding pads are bonded to the plurality of first upper electrode bonding pads, respectively, and the plurality of second lower electrode bonding pads are bonded to the plurality of second upper electrode bonding pads, respectively.

A semiconductor chip may include: a semiconductor substrate; a through silicon via that vertically penetrates the semiconductor substrate; an integrated device layer on a first surface of the semiconductor substrate and including integrated devices; a multi-wiring layer on the integrated device layer and including layers of wires; an upper metal layer on the multi-wiring layer and connected to the wires; and a lower metal layer on a second surface of the semiconductor substrate. The semiconductor substrate may include a lower bump area on the second surface of the semiconductor substrate, the lower bump area including bump pads thereon, and the lower metal layer may be on a periphery of the lower bump area.

An electronics assembly includes a plurality of planar conductive metal sheets including a first conductive metal sheet, a second conductive metal sheet attached and electrically coupled to the first metal sheet, and a third conductive metal sheet attached and electrically coupled to the second metal sheet. The second metal sheet is located between the first and third conductive metal sheets. Air gaps are defined in the plurality of planar conductive metal sheets to form metal traces that define electrically isolated conductive paths from an outer surface of the first conductive metal sheet to an outer surface of the third conductive metal sheet in a multilevel conductive wiring network. The multilevel conductive wiring network can be attached and electrically coupled to a microchip and to one or more capacitors to form a power converter.

An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.

The disclosure provides an electronic device and a manufacturing method thereof. The electronic device includes a package structure, a circuit structure, a bonding structure and an external element. The circuit structure is disposed on the package structure and is electrically connected to the package structure. The circuit structure has a recess. The bonding structure includes a first bonding pad and a second bonding pad. The second bonding pad is disposed in the recess, and the second bonding pad is disposed on the first bonding pad. The bonding structure is disposed between the circuit structure and the external element. The external element is electrically connected to the circuit structure through the bonding structure. A width of the first bonding pad is smaller than a width of the second bonding pad.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. A semiconductor structure includes a first chip. The first chip includes a first interconnect layer, a first conductive layer disposed on the first interconnect layer, a first dielectric layer covering the first conductive layer, and a first bonding pad embedded in the first dielectric layer and extending into the first conductive layer. The method of manufacturing the semiconductor structure includes the following operations. A first conductive layer is formed on a first interconnect layer. A first dielectric layer is formed on the first conductive layer and the first interconnect layer. The first dielectric layer is etched to form a first trench on the first conductive layer. A portion of the first conductive layer is etched to form a second trench. A first bonding pad is formed in the second trench.

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.