A transistor includes a semiconductor die with an active region and one or more non-active regions that do not overlap or overlie the active region. The transistor further includes a group of multiple transistor fingers in the active region. One or more source vias are located adjacent to sides of the group of transistor fingers. One or more source manifolds are located in the non-active region(s), and the source manifold(s) electrically connect the source via(s) with at least one source region of the multiple transistor fingers.

One example includes a method for fabricating a substrate-integrated waveguide (SIW). The method includes forming a first metal layer on a carrier surface. The first metal layer can extend along an axis. The method also includes forming a first metal sidewall extending from a first edge of the first metal layer along the axis and forming a second metal sidewall extending from a second edge of the first metal layer opposite the first edge along the axis to form a trough extending along the axis. The method also includes providing a dielectric material over the first metal layer and over the first and second metal sidewalls. The method further includes forming a second metal layer over the dielectric material and over the first and second metal sidewalls. The second metal layer can extend along the axis to enclose the SIW in all radial directions along the axis.

A semiconductor structure including a substrate, a conductive layer, and a semiconductor device is provided. The substrate includes a first surface, a second surface opposite to the first surface, at least one insulating vacancy extending from the first surface toward the second surface, and a through hole passing through the substrate. The conductive layer fills in the through hole. The semiconductor device is disposed on the second surface and is electrically connected to the conductive layer, and the at least one insulating vacancy is distributed corresponding to the semiconductor device.

Disclosed in the present invention are an electromagnetic shielding structure, a manufacturing method and a communication terminal. The electromagnetic shielding structure comprises a module substrate, which is formed with a plurality of grounding holes penetrating through the module substrate, and the plurality of grounding holes jointly define a mounting area; a device to be shielded, which is attached to the module substrate and located in the mounting area; a plurality of grounding bonding pads, which are respectively arranged in the grounding holes in a penetrating manner; and a plurality of wires, wherein the two ends of each wire are respectively connected to two different grounding bonding pads, such that the plurality of wires jointly form a shielding layer erected above the device to be shielded.

A three-dimensional fan-out integrated package structure, a packaging method thereof, and a wireless headset are disclosed. The three-dimensional fan-out integrated package structure includes a first rewiring layer, a second rewiring layer, a metal connection pillar, a first semiconductor chip, a second semiconductor chip, a first filler layer, a first encapsulating layer, a functional chip, a second filler layer, a second encapsulating layer, and metal bumps. By stacking two semiconductor chips, the structure can effectively reduce the packaging area and realize device packaging with high density and high integration, while enabling the minimum line width/line spacing to be reduced to 1.5 m/1.5 m. In addition, the three-dimensional fan-out integrated package structure can simultaneously integrate various functional chips and components such as GPU/PMU/DDR/mm-wave antenna/capacitor/inductor/transistor/flash memory/filter to realize system-level packaging, which not only can reduce cost but also improve the effectiveness of the package structure by using physical isolation to reduce device interference.

A high-frequency module includes a first module substrate including first and second major surfaces, and a second module substrate including third and fourth major surfaces. The first major surface (faces the second major surface. Electronic components are disposed between the second and third major surfaces, on the first major surface, and on the fourth major surface. External connection terminals are disposed on the fourth major surface. A recess is formed in the first major surface. The electronic components include a first electronic component and a second electronic component (shorter in height than the first electronic component. The first electronic component is disposed in the recess, and the second electronic component is disposed in a region outside of the recess on the first major surface.

A semiconductor structure including: a substrate including a plurality of conductive layers and a plurality of insulating layers stacked alternately with each other along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the conductive layers to a bottom conductive layer of the conductive layers and including a first capacitive structure, the first capacitive structure extending in a first conductive layer of the conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in the first conductive layer or a second conductive layer of the conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

A phase change material switching circuit may be provided by forming a semiconductor circuit including a power amplifier and a low noise amplifier on a substrate; forming metal interconnect structures embedded in first dielectric material layers over the power amplifier and the low noise amplifier; forming a first phase change material (PCM) switch and a second PCM switch over the first dielectric material layers, wherein the first PCM switch includes a first electrode and a second electrode, and the second PCM switch includes a third electrode and a fourth electrode, wherein the second electrode is electrically connected to the third electrode to form a common electrical node; and electrically connecting a radio-frequency (RF) antenna to the common electrical node.

A method of marking information on a substrate for use in a semiconductor component is provided. The method comprises providing a substrate for use in a semiconductor component, providing a metal layer on a surface of the substrate, and providing a marking within the metal layer. A method of making a die, a radio-frequency module and a wireless mobile device; as well as a substrate, a die, a radio-frequency module and a wireless mobile device is also provided.