A package for a semiconductor device includes a metal base plate, a wall portion, a first metal film, and a lead portion. The base plate has a first region and a second region surrounding the first region. The wall portion has a first frame body comprising metal and a second frame body comprising resin. The first frame body is provided on the second region. The second frame body is provided on the first frame body. The first metal film is provided on the second frame body. The lead portion is conductively bonded to the first metal film. The first frame body is conductively bonded to the base plate. A thickness of the first frame body in a first direction that is a direction in which the first frame body and the second frame body are arranged is larger than a thickness of the first metal film in the first direction.

A semiconductor device has a substrate and an electrical component disposed over the substrate. A heat spreader with a plasma-enhanced surface is disposed over the electrical component. A TIM is disposed between the electrical component and plasma-enhanced surface of the heat spreader. The TIM can be deposited on the electrical component or plasma-enhanced surface. The plasma-enhanced surface contains argon ions and oxygen ions. The heat spreader is disposed in a reaction chamber. Reactant gases, such as argon and oxygen, are introduced into the reaction chamber. An electric field is formed within the reaction chamber to ionize the argon and oxygen and form the plasma-enhanced surface. The plasma-enhanced surface has properties of roughness and tacky-ness or adhesive property by nature of the surface exhibiting a chemical bonding group. An underfill material is deposited between the electrical component and substrate. The electrical component can be a flipchip type semiconductor die.

A joined body production method includes subjecting a first electronic component and a second electronic component to thermocompression bonding via a hot-melt adhesive sheet. The hot-melt adhesive sheet includes a binder and solder particles. The binder includes a crystalline polyamide resin having a carboxyl group. A melting point of the solder particles is 30 C. to 0 C. lower than a temperature of the thermocompression bonding. When melt viscosities of the hot-melt adhesive sheet are measured under a condition of a heating rate of 5 C./min., the hot-melt adhesive sheet has a ratio of a melt viscosity at 40 C. lower than the temperature of the thermocompression bonding to a melt viscosity at 20 C. lower than the temperature of the thermocompression bonding of no less than 10.

A semiconductor device with a two-sided redistribution layer is disclosed. The semiconductor device comprises a host device and one or more memory stack cubes. A redistribution layer is disposed between and couples the host device and the memory stack cubes. This redistribution layer features an edge surface extending between the host device and the memory stack cubes. The semiconductor device includes first connective circuitry that extends through the redistribution layer, is coupled with the host device, and is exposed at the edge surface of the redistribution layer. Additionally, second connective circuitry extends through the redistribution layer, is coupled with the memory stack cubes, and is exposed at the edge surface of the redistribution layer. Connective structures couple the first and second connective circuitry exposed at the edge surface of the redistribution layer.

Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates. The architecture facilitates ASIC, ASSP, and FPGA ICs and neural networks, reducing footprint and power requirements.

In a general aspect, mechanisms for dual coupling of a semiconductor package assembly to a component includes a thermal dissipation appliance; a semiconductor package assembly bonded to the thermal dissipation appliance by a thermally conductive adhesive material; and at least one clamping tool mechanically coupled to the semiconductor package assembly and to the thermal dissipation appliance, the at least one clamping tool exerting a compressive force on the semiconductor package assembly to maintain an interface between the semiconductor package assembly and the thermal dissipation appliance.

A method includes forming a package component, including forming a thermal via extending through a substrate; and bonding a die to the thermal via; attaching the thermal via of the package component to a first conductive pad of a package substrate, wherein the package substrate includes a heat pipe underneath the first conductive pad; and attaching a support structure to a second conductive pad of the package substrate, wherein the heat pipe is underneath the second conductive pad, wherein the support structure includes a first thermoelectric cooler.

A semiconductor package includes: a molded body having opposite first and second sides; at least one semiconductor die encapsulated by the molded body; and a die carrier having opposite first and second sides. The semiconductor die is arranged over the first side of the die carrier. The second side of the die carrier is at least partially exposed from the second side of the molded body, forming at least one exposed portion of the die carrier. The first side of the molded body includes a first portion protruding from a second portion in a vertical direction perpendicular to the first side, forming a planar surface. The second portion extends completely along at least one edge of the first side. A center point of the first portion is in vertical alignment with a center point of the exposed portion.

A package and method is disclosed. In one example, the package comprises a component assembly section, at least one electronic component being assembled with the component assembly section, at least one lead section being electrically coupled with the at least one electronic component and/or with the component assembly section, an encapsulant at least partially encapsulating the at least one electronic component and partially encapsulating the component assembly section and the at least one lead section so that part of the component assembly section and part of the at least one lead section are exposed beyond the encapsulant. A thermoplastic structure covers an exposed area of the component assembly section without covering an exposed area of the at least one lead section.

A semiconductor module arrangement comprises a substrate (10), a base plate or heat sink (30), and a layer (40) arranged between the substrate (10) and the base plate or heat sink (30), wherein the layer (40) comprises a liquid or viscous thermal interface material, TIM, (42) a plurality of filler particles (44) distributed within the liquid or viscous thermal interface material, TIM, (42) and a plurality of capsules (46) distributed within the liquid or viscous thermal interface material, TIM, (42) wherein each of the plurality of capsules (46) comprises a catalyst, or radical initiator, and the plurality of capsules (46) are configured to release the catalyst, or radical initiator when being activated, wherein the plurality of capsules (46) are configured to be activated at increased temperatures or under increased pressure.