A method for forming a semiconductor structure includes forming a conductive structure in a first dielectric layer, the conductive structure including an terminal portion and an extending portion, forming a second dielectric layer on the first dielectric layer, forming a first opening through the second dielectric layer directly above the extending portion and a second opening through the second dielectric layer directly above the terminal portion, a width of the second opening being smaller than 50% of a width of the first opening, forming a conductive material layer on the second dielectric layer and filling the first opening and the second opening, and performing a chemical mechanical polishing process to remove the conductive material layer outside the first opening and the second opening to obtain a conductive via in the first opening and a dummy via in the second opening.

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion directly and physically connected to the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, a dummy via through the second dielectric layer and directly contacting the terminal portion, wherein the dummy via comprises a lower portion consisting of a first filling layer and an upper portion consisting of a second filling layer, wherein the first filling layer and the second filling layer comprise different materials.

Various embodiments of interconnect structures and methods of forming interconnect structures used in an integrated circuit (IC) device are provided in the present disclosure. More specifically, techniques are provided for forming low-resistivity interconnect structures including a multilayer interconnect film stack comprising a first conductive film formed beneath and in contact with a second conductive film. The presence of the first conductive film within the multilayer interconnect film stack decreases the resistivity of the second conductive film when the second conductive film is deposited onto the first conductive film to provide a low-resistivity interconnect structure.

Semiconductor devices and a method for manufacturing the semiconductor devices are provided. The method includes forming a plurality of bit-line structures on a chip region of a substrate, forming a first alignment key pattern on a scribe line region of the substrate, forming a first alignment key trench in at least a portion of the first alignment key pattern, forming a landing pad layer between the plurality of bit-line structures and on top surfaces of the plurality of bit-line structures, forming a gap-fill layer on the landing pad layer and in an unoccupied portion of the first alignment key trench and performing a planarization process on the gap-fill layer and the landing pad layer.

A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.

A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.

The present disclosure provides a method of forming a semiconductor structure. The method includes the following operations. A first hard mask stack is formed on a dielectric layer, in which the dielectric layer includes an array region. The first hard mask stack is etched to form a second hard mask stack and a first trench extending along a first direction above the array region and in the second hard mask stack. A second trench is formed in the second hard mask stack extending along a second direction different from the first direction, in which the first trench and the second trench cross each other to form an intersection. The second hard mask stack and the dielectric layer directly below the intersection are etched to form a through-hole. A first landing pad is formed in the through-hole.

A semiconductor device includes: a first conductive structure that comprises a first portion having sidewalls and a bottom surface, wherein the first conductive structure is embedded in a first dielectric layer; and an isolation layer comprising a first portion and a second portion, wherein the first portion of the isolation layer lines the sidewalls of the first portion of the first conductive structure, and the second portion of the isolation layer lines at least a portion of the bottom surface of the first portion of the first conductive structure.

An integrated circuit device includes a middle insulating structure on a substrate, a first contact structure passing through the middle insulating structure and extending by a first vertical length from a top surface of the middle insulating structure toward the substrate, and a second contact structure passing through the middle insulating structure. The middle insulating structure may have a top surface extending in a lateral direction at a first vertical level. The second contact structure may extend by a second vertical length greater than the first vertical length from the top surface of the middle insulating structure toward the substrate. The first contact structure may have a first top surface extending planar along an extension line of the top surface of the middle insulating structure. The second contact structure may have a second top surface, which may be convex in a direction away from the substrate.

An apparatus that includes a first conductive pattern positioned at a first wiring layer and extending in a first direction, a second conductive pattern positioned at a second wiring layer located above the first wiring layer and extending in a second direction crossing the first direction, and a contact plug connecting the first conductive pattern with the second conductive pattern. The contact plug includes a lower conductive section contacting the first conductive pattern and an upper conductive section contacting the second conductive pattern. A maximum width of the upper conductive section in the first direction is smaller than a maximum width of the lower conductive section in the first direction.