A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a <111> grain orientation normal to a horizontal surface of the structure.

A method for manufacturing a semiconductor device is provided. The method includes the following steps. First, a first semiconductor structure and a second semiconductor structure are provided. The first semiconductor structure includes a first conductive pillar and a first conduction layer connected to the first conductive pillar, and the second semiconductor structure includes a second conductive pillar and a second conduction layer connected to the second conductive pillar, wherein a material of the first conduction layer and a material of the second conduction layer are conductive material and are volatilizable at a predetermined temperature. Thereafter, the first semiconductor structure and the second semiconductor structure are bonded to combine the first conductive pillar with the second conductive pillar. After the step of bonding the first semiconductor structure and the second semiconductor structure is completed, the first conduction layer and the second conduction layer are disappeared.

A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.

Disclosed herein are methods of forming a microelectronic component. In some embodiments, the method includes providing a substrate, forming a metal feature over the substrate, forming an organic dielectric layer over the element such that the organic dielectric layer covers sidewalls of the metal feature, forming an inorganic dielectric material over the organic dielectric layer, and planarizing the inorganic dielectric material, the organic dielectric layer, and the metal feature. The planarized surface can serve as a hybrid bonding surface. The metal feature is exposed at the hybrid bonding surface.

A method of manufacturing interconnects for an electronic device includes the steps: a) providing a substrate having a first die, assembled to a second die by hybrid bonding, formed therein, and having conductive areas positioned on top of it, the second die comprising through silicon vias; b) forming conductive wires on the conductive areas, and optionally on the through silicon vias; c) depositing a layer of insulating material on the substrate and on the second die, to encapsulate the conductive wires; d) thinning the layer of insulating material; and e) forming conductive elements on the layer of insulating material, the conductive elements being connected either to the conductive areas or to the vias.

An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.

A semiconductor structure includes a first conductive element having a first side, a second conductive element having a second side contacting the first side of the first conductive element; and a blocking member, surrounded by the first conductive element and adjacent to the second conductive element. A first width of the first side is substantially greater than a second width of the second side, and at least a portion of the first conductive element is disposed between the second conductive element and the blocking member. A method of manufacturing a semiconductor structure, includes providing a dielectric; patterning the dielectric to form a first opening having a first portion and a second portion connected to the first portion, wherein a blocking member is disposed within the first portion; disposing a first conductive element and a second conductive element into the first portion and the second portion of the first opening respectively.

A method for manufacturing a semiconductor stack structure with ultra thin dies includes manufacturing a plurality of semiconductor wafers. A carrier board is bonded to the redistribution layer of one of the semiconductor wafers, then the second substrate part and the stop layer structure are removed to expose the first substrate part, and the wafer conductive structures are penetrated thereon and connected to the redistribution layer. By thinning the first substrate part, the wafer conductive structures are protruded, and a bonding dielectric layer is formed to cover the wafer conductive structures and is thinned to expose the wafer conductive structure. A bonding layer with conductive pillars is formed on the redistribution layer of another semiconductor wafer, and a die sawing is performed to form a plurality of batches of dies. The bonding layers of a batch of dies are bonded to the bonding dielectric layer by using hybrid bonding technology.

A microelectronic assembly and a method of forming same. The assembly includes: first and second microelectronic structures; and an interface layer between the two microelectronic structures including dielectric portions in registration with dielectric layers of each of the microelectronic structures, and electrically conductive portions in registration with electrically conductive structures of each of the microelectronic structures, wherein the dielectric portions include an oxide of a metal, and the electrically conductive portions include the metal.

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.