In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

A method for manufacturing a semiconductor device includes: forming an adhesion layer on an interconnect structure disposed over a substrate; forming a plurality of conductive interconnects on the adhesion layer, the plurality of conductive interconnects being spaced apart from each other so as to form a plurality of trenches among the plurality of conductive interconnects and to expose a plurality of portions of the adhesion layer through the plurality of trenches, respectively; and forming the plurality of portions of the adhesion layer into a molecular organic framework layer such that the molecular organic framework layer fills the plurality of trenches.

Microelectronic deviceshaving at least one conductive contact structure adjacent a silicide regionare formed using methods that avoid unintentional contact expansion and contact reduction. A first metal nitride liner is formed in a contact opening, and an exposed surface of a polysilicon structure is thereafter treated (e.g., cleaned and dried) in preparation for formation of a silicide region. During the pretreatments (e.g., cleaning and drying), neighboring dielectric material is protected by the presence of the metal nitride liner, inhibiting expansion of the contact opening. After forming the silicide region, a second metal nitride liner is formed on the silicide region before a conductive material is formed to fill the contact opening and form a conductive contact structure (e.g., a memory cell contact structure, a peripheral contact structure).

There is provided a technique that includes (a) supplying a first-element-containing gas to the substrate; (b) supplying a first reducing gas to the substrate; (c) supplying a second reducing gas, which is different from the first reducing gas, to the substrate; (d) supplying a third reducing gas, which is different from both the first reducing gas and the second reducing gas, to the substrate; (e) after a start of (a), performing (b) in parallel with (a); (f) in (e), performing (d) in parallel with (b); and (g) forming a first-element-containing film on the substrate by alternately performing (e) and (c) a predetermined number of times.

Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

Embodiments of this disclosure provide a semiconductor structure, including an active area disposed in a substrate, a gate structure disposed on the active area, two source/drain regions disposed in the substrate on both sides of the gate structure, two bit line contacts disposed on the both sides of the gate structure, a first dielectric layer surrounding an upper portion of the gate structure and a second dielectric layer surrounding an upper portion of each of the two bit line contacts. Each of the two bit line contacts directly contacts a portion of each of the two source/drain regions. Additionally, a method of manufacturing a semiconductor structure is also provided in this disclosure.

In some embodiments, an interconnect structure includes a first conductive structure disposed in a first dielectric layer, wherein the first conductive structure includes a first barrier layer and a first main conductive layer; a second dielectric layer disposed over the first dielectric layer; and a second conductive structure disposed in the second dielectric layer and over the first conductive structure, wherein the second conductive structure includes: a second barrier layer including a first conductive material selected from Ru or Mo; a second main conductive layer disposed over the second barrier layer and including a second conductive material; and a third conductive material being a dopant doped in the second main conductive layer or being a continuous layer between the second main conductive layer and the second barrier layer, wherein the third conductive material is selected from Mn, Ti, Co, Ru, Al, Zn, In, or combinations thereof.

In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.

Methods of depositing metal nitride layers employing low temperature cyclical deposition processes including cyclic compounds are disclosed. The cyclical deposition processes include repeatedly performing a deposition cycle including introducing a metal precursor into a reaction chamber, introducing a nitrogen reactant into the reaction chamber, and introducing a reducing agent comprising a cyclic compound into the reaction chamber. Metal nitride layers and semiconductor structures including metal nitride layers are also disclosed.