One example includes a method for fabricating an integrated circuit (IC) device. The method includes fabricating a semiconductor die comprising a metal top (METTOP) structure and forming a barrier layer over the METTOP structure to cover approximately the entirety of the METTOP structure. The method also includes forming a polyimide (PI) layer over the semiconductor die and over a portion of the barrier layer to form a gap that exposes the barrier layer through the PI layer. The method further includes forming a conductive post in the gap over the barrier layer.

A semiconductor device includes a first semiconductor chip having a first surface and a second surface that is opposite to the first surface, a second semiconductor chip having a third surface facing the first surface and a fourth surface that is opposite to the third surface, a first dielectric layer on the first surface of the first semiconductor chip, a second dielectric layer on the third surface of the second semiconductor chip, a connection pad including a first conductive pad penetrating the first dielectric layer and a second conductive pad penetrating the second dielectric layer, and an adhesive layer between the first dielectric layer and the second dielectric layer, where the adhesive layer includes an organic dielectric material, the first conductive pad and the second conductive pad extend into the adhesive layer, and the first conductive pad directly contacts the second conductive pad.

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a pad on a semiconductor chip, a protective layer on the semiconductor chip and having an opening that exposes a portion of a top surface of the pad, and a bump structure electrically connected to the pad. The bump structure includes a metal layer on the pad and a solder ball on the metal layer. A first width of the metal layer is about 0.85 times to about 0.95 times a second width of the opening.

A semiconductor package includes; a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes; a first substrate, a first bonding pad on a first surface of the first substrate, and a first passivation layer on the first surface of the first substrate exposing at least a portion of the first bonding pad. The second semiconductor chip includes; a second substrate, a second insulation layer on a front surface of the second substrate, a second bonding pad on the second insulation layer, a first alignment key pattern on the second insulation layer, and a second passivation layer on the second insulation layer, covering at least a portion of the first alignment key pattern, and exposing at least a portion of the second bonding pad, wherein the first bonding pad and the second bonding pad are directly bonded, and the first passivation layer and the second passivation layer are directly bonded.

A described example includes: a semiconductor die having a device side surface and an opposing backside surface, the backside surface mounted to a die pad of a lead frame, the lead frame comprising conductive leads spaced from the die pad; a conductor layer overlying the device side surface; bond pads including bond pad conductors formed in the conductor layer, a nickel layer over the bond pad conductors, and a palladium or gold layer over the nickel layer; conductor traces formed in the conductor layer, the conductor traces free from the nickel layer and the palladium or gold layer; bond wires bonded to the bond pads electrically coupling the bond pads to conductive leads; and mold compound covering the semiconductor die, the bond pads, the bond wires, and portions of the lead frame, wherein portions of the conductive leads are exposed from the mold compound to form terminals.

An image pickup unit includes: an image pickup substrate including a first principal surface and a second principal surface, a light receiving circuit being formed on the first principal surface and a through wiring being placed on an inner surface of a via hole including an opening in the second principal surface; a solder resist film placed around the via hole on the second principal surface and in the via hole in a range from a bottom face to a level not reaching the second principal surface; and a bonding terminal which is made of solder, covers a surface of the solder resist film placed in the via hole, and is bonded to the through wiring on an outer edge of the opening in the via hole, the through wiring being not covered with the solder resist film.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

A method for manufacturing a semiconductor package includes forming a first semiconductor chip having a first bonding surface, the first semiconductor chip including a first outermost insulating layer providing the first bonding surface, a first internal insulating layer on the first outermost insulating layer, a first external marks within the first outermost insulating layer, and a first internal mark within the first internal insulating layer. The first external marks include a first pattern having a first center portion and a second pattern having a first ring portion surrounding the first center portion when viewed in a plan view, the first internal mark is disposed between the first center portion and the first ring portion when viewed in the plan view, and the first external marks and the first internal mark together form a first alignment structure.

A backlight unit and a display device including the same are disclosed. More specifically, a backlight unit is disclosed that includes a plurality of light sources disposed on a glass substrate and disposed in a plurality of rows and a plurality of columns, and first and second transistors disposed on the glass substrate and spaced apart from each other, wherein each of the first transistor and the second transistor is disposed so as not to overlap the plurality of light sources disposed at points where two rows and two columns cross each other. Thus, image quality is excellent.

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.