A semiconductor device of an embodiment includes: a first semiconductor element; a first insulating resin that seals the first semiconductor element; a wiring substrate having a pad; a first wiring that extends from the first semiconductor element toward the wiring substrate, and has a first head portion and a first column portion, the first column portion connected to the first semiconductor element and the first head portion exposed on a surface of the first insulating resin; and a first conductive bonding agent that electrically connects the first head portion of the first wiring and the pad. When a surface of the first head portion facing a side of the first insulating resin is defined as a first surface. A surface of the first insulating resin on a side of the wiring substrate is defined as a second surface. A distance from a surface of the wiring substrate on a side of the first insulating resin to the first surface is defined as a first distance, and a distance from a surface of the wiring substrate on the side of the first insulating resin to the second surface is defined as a second distance. The first distance is shorter than the second distance.

Various aspects of the present disclosure generally relate to integrated circuit devices, and to a conductive structure with multiple support pillars. A device includes a die including a contact pad. The device also includes a conductive structure. The conductive structure includes multiple support pillars coupled to the die, a bridge coupled to each of the multiple support pillars, and a cap pillar coupled to the bridge opposite the multiple support pillars. The device further includes a solder cap coupled to the cap pillar. The solder cap is electrically connected to the contact pad via the cap pillar, the bridge, and at least one of the multiple support pillars.

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a panel-level chip packaging structure and method based on a steel plate platform. The packaging structure includes: a steel plate; a gold-nickel layer plated on the steel plate, where the gold-nickel layer is provided with upwardly protruding pins corresponding to a chip; the chip flipped to the corresponding pins; and a molded body coating the corresponding chip and the gold-nickel layer. According to the packaging structure and method of the present disclosure, an overall thickness of a chip-packaged product can be reduced. A wire bonding process and an electroplating process are further omitted, so that the overall thickness of chip packaging can be further reduced. An ultra-thin packaging structure can be implemented, the chip packaging efficiency can further be improved, and a complete-process chip packaging cycle can be shortened.

An electronic package is provided in which an electronic structure is bonded onto a carrier structure via a plurality of conductive elements, where each of the conductive elements is connected to a single contact of the electronic structure via a plurality of conductive pillars. Therefore, when one of the conductive pillars fails, each of the conductive elements can still be electrically connected to the contact via the other of the conductive pillars to increase electrical conductivity.

Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a substrate, a first integrated circuit die over the substrate including a first recess that penetrates into a first edge of the first integrated circuit die, and a second integrated circuit die over the first integrated circuit die including a second recess that penetrates into a second edge of the second integrated circuit die. The semiconductor device assembly includes a pillar structure that uses the first recess and the second recess to align perimeters of the first integrated circuit die and the second integrated circuit die.

A semiconductor package comprises a first die having a central region and a peripheral region that surrounds the central region; a plurality of through electrodes that penetrate the first die; a plurality of first pads at a top surface of the first die and coupled to the through electrodes; a second die on the first die; a plurality of second pads at a bottom surface of the second die, the bottom surface of the second die facing the top surface of the first die; a plurality of connection terminals that connect the first pads to the second pads; and a dielectric layer that fills a space between the first die and the second die and surrounds the connection terminals. A first width of each of the first pads in the central region may be greater than a second width of each of the first pads in the peripheral region.

A connection panel unit and a display device including the same are disclosed. The connection panel unit includes a connection panel having a chip coupling region and a link region, a pad coupled to the chip coupling region, and a display driver chip coupled to the pad. The chip coupling region includes an input region and an output region spaced apart from each other. The pads include input pads coupled to the input region and output pads coupled to the output region. The ratio of pressure applied to the output pads to the pressure applied to the input pads may be between 0.9 and 1.1. The present disclosure can form an improved contact between a display driver chip and a connection panel.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A semiconductor structure includes a semiconductor chip, a substrate and a plurality of bump segments. The bump segments include a first group of bump segments and a second group of bump segments collectively extended from an active surface of the semiconductor chip toward the substrate. Each bump segment of the second group of bump segments has a cross-sectional area greater than a cross-sectional area of each bump segment of the first group of bump segments. The first group of bump segments includes a first bump segment and a second bump segment. Each of the first bump segment and the second bump segment includes a tapered side surface exposed to an environment outside the bump segments. A portion of a bottom surface of the second bump segment is stacked on the first bump segment, and another portion of the bottom surface of the second bump segment is exposed to the environment.