A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

In a bonding process of a flip chip bonding method, a chip is bonded to contact pads of a substrate by composite bumps which each includes a raiser, a UBM layer and a bonding layer. Before the bonding process, the surface of the bonding layer facing toward the substrate is referred to as a surface to be bonded. During the bonding process, the surface to be bonded is boned to the contact pad and become a bonding surface on the contact pad. The bonding surface has an area greater than that of the surface to be bonded so as to reduce electrical impedance between the chip and the substrate.

A manufacturing method for a semiconductor device according to an embodiment includes a first step deforming a bump of a semiconductor element by applying a first load to the semiconductor element to press the bump onto a circuit board and applying either no ultrasonic vibration or ultrasonic vibration with a first strength to the bump and a second step, after the first step, bonding the bump to a pad of the circuit board by applying a second load to the semiconductor element to press the bump and applying ultrasonic vibration with a second strength stronger than the first strength to the bump.

The present disclosure provides a chip package device. An example chip package device includes: at least one connection pad on a first surface of the chip; at least one pillar extending from, and in contact with, the pad; the pillar being formed in an alloy of a first element and of a second element, a melting temperature of the alloy being greater than a melting temperature of at least one of the first and second elements and greater than 260 C.

A semiconductor package may include: a first wiring structure including a first wiring pattern and a first wiring insulating layer surrounding the first wiring pattern; a first semiconductor chip above the first wiring structure; a second semiconductor chip above the first wiring structure and spaced apart from the first semiconductor chip in a horizontal direction; an adhesive layer including a first portion on an upper surface of the first semiconductor chip, and further including a second portion on an upper surface of the second semiconductor chip; a molding member on the first wiring structure and surrounding side surfaces of each of the first semiconductor chip, the second semiconductor chip, and the adhesive layer; and a heat dissipation member on an upper surface of each of the molding member and the adhesive layer.

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.

Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a substrate having a first substrate alignment structure. The semiconductor structure may also include a first die with a first die alignment structure. The first die may be attached to the substrate with the first substrate alignment structure matched to the first die alignment structure.

A chip-size-package type semiconductor device includes a semiconductor layer, pads, and metal redistributions that are located above a top surface of the semiconductor layer and each of which is connected to one or more pads. The metal redistributions include first metal redistributions each of which includes a first portion and a second portion contained within the first portion in a plan view, the second portion being located above the first portion and having an area smaller than an area of the first portion in the plan view. Each of the first metal redistributions includes one or more line-shaped bends in a boundary portion between the first portion and the second portion on a surface of the first metal redistribution, the one or more line-shaped bends each having an interior angle of at least 180 degrees in a cross section of the first metal redistribution.

A driving substrate, a micro LED transfer device and a micro LED transfer method are provided. A side surface of the driving substrate is arranged with a binding metal layer, a positioning layer is arranged around the binding metal layer, and a width of the positioning layer at a position away from the driving substrate is less than that a width at a position close to the driving substrate.