A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Aspects and embodiments disclosed herein include a semiconductor device comprising a metal-insulator-metal capacitor having a capacitance. The metal-insulator-metal capacitor comprises a plurality of metal-insulator-metal capacitors coupled in parallel, each metal-insulator-metal capacitor of the plurality of metal-insulator-metal capacitors having a top plate, a bottom plate, and a corresponding capacitance, and a plurality of bottom contacts, at least one of the plurality of bottom contacts arranged between a pair of directly adjacent metal-insulator-metal capacitors of the plurality of metal-insulator-metal capacitors. Also disclosed are antennaplexers, electronic device modules, and electronic devices including aspects and embodiments of the semiconductor device.

A semiconductor device has a substrate and encapsulant deposited over the substrate. An electrical connector is disposed over the substrate outside the encapsulant. An antenna can be formed over the substrate. A first shielding material is disposed over a portion of the encapsulant without covering the electrical connector with the first shielding material. The first shielding material is disposed over the portion of the encapsulant and the portion of the substrate using a direct jet printer. A cover is disposed over the electrical connector. A second shielding material is disposed over the encapsulant to prevent the second shielding material from reaching the electrical connector. The second shielding material overlaps the first shielding material and covers a side surface of the encapsulant and a side surface of the substrate. The cover is removed to expose the electrical connector free of shielding material.

A method of fabricating an electronic device including fabricating a multilevel package substrate with first, second, third, and fourth levels, a semiconductor die mounted to the first level, and fabricating a conductor backed coplanar waveguide transmission line feed with an interconnect and a conductor, the interconnect including coplanar first, second, and third conductive lines extending in the first level along a first direction from respective ends to an antenna, the second and third conductive lines spaced apart from opposite sides of the first conductive line along an orthogonal second direction, and the conductor extending in the third level under the interconnect and under the antenna.

A fan-out wafer level packaging (FOWLP) unit which includes a substrate, a first dielectric layer, at least one antenna, at least one die, a second dielectric layer, at least one conductive pillar, a plurality of first conductive circuits, a third dielectric layer, a plurality of second conductive circuits, and an outer protective layer is provided. The first conductive circuits and the second conductive circuits are produced by filling a metal paste into slots and grinding the metal paste. The die is electrically connected with the antenna. The die is electrically connected to the outside through bonding pads around a chip area on a second surface of the die. Thereby the FOWLP unit is formed and problems of the FOWLP module or technology available now generated during manufacturing of the respective conductive circuits including higher manufacturing cost and less environmental benefit can be solved.

A display substrate has a display area and a peripheral area adjacent to the display area. The display substrate includes; a substrate; an antenna wiring disposed on a side of the substrate; the antenna wiring being located in the peripheral area and arranged around the display area; and at least one conductive layer located on the side of the substrate. The antenna wiring is arranged in a same layer as the at least one conductive layer.

A semiconductor device includes a substrate including a conductive transceiver pattern proximate to the substrate top side. An antenna structure includes an antenna dielectric structure coupled to the substrate top side, an antenna conductive structure having an antenna element, and a cavity below the antenna element. The antenna element overlies the conductive transceiver pattern. The cavity includes a cavity ceiling, a cavity base, and a cavity sidewall. Either a bottom surface of the antenna element defines the cavity ceiling and a perimeter portion of the antenna element is fixed to the antenna dielectric structure, or the antenna dielectric structure includes a body portion having a bottom surface that defines the cavity ceiling and the antenna element is vertically spaced apart from the bottom surface of the body portion. A semiconductor component is coupled to the substrate bottom side and the transceiver pattern.

A device includes a high frequency chip and a dielectric material arranged between a first area radiating an electromagnetic interference signal in a first frequency range between 1 GHz and 1 THz and a second area receiving the electromagnetic interference signal. An attenuation of the dielectric material is more than 5 dB/cm at least in a subrange of the first frequency range.

This invention provides opportunity for diamond and bi-wafer microstructures to be implemented in advanced ICs and advanced IC packages to form a new breed of ICs and SiPs that go beyond the limitations of silicon at the forefront of IC advancement due primarily to diamond's extreme heat dissipating ability. Establishing the diamond and bi-wafer microstructure capabilities and implementing them in advanced ICs and advanced IC packages gives IC and package architects and designers an extra degree of design freedom in achieving extreme IC performance, particularly when thermal management presents a challenge. Diamond's extreme heat spreading ability can be used to dissipate hotspots in processors and other high-power chips such as GaN HEMT, resulting in performance and reliability enhancement for IC and package applications covering HPC, AI, photonics, 5G RF/mmWave, power and IoT, and at the system level propelling the migration from traditional computing to near-memory computing and in-memory computing.

A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die have an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film.