A semiconductor package structure is provided. The structure includes a package substrate having a first surface and a second surface opposite to the first surface and including a ground layer embedded therein. A semiconductor die is formed on the first surface of the package substrate and an antenna pattern layer is formed on the second surface of the package substrate and electrically coupled to the semiconductor die. The structure also includes a first connector and a second connector formed on the second surface of the package substrate and arranged adjacent to the antenna pattern layer. The first connector is electrically coupled to the semiconductor die and electrically isolated to the ground layer, and the second connector is electrically coupled to the ground layer. A wireless communication device including the semiconductor package structure is also provided.

An integrated circuit is formed by a semiconductor part with a semiconductor substrate and an interconnection part including levels of metals. An electrostatic-discharge sensor includes a semiconductor structure in the semiconductor part and a network of metal antennas in the interconnection part. The electrostatic-discharge sensor has at least one pair of two nodes having one of a resistive link or a capacitive link or a PN-junction link in the semiconductor structure. The antennas of the network of antennas coupled to the nodes of the least one pair of two nodes exhibit an asymmetry in one or more of shape and size.

An antenna module includes a first substrate, a second substrate, the second substrate including at least one cavity at one of the first main surface. The first substrate includes at least an RF antenna element and/or an RF chip and/or an RF conductive trace, which are arranged on the first main surface of the substrate. The first substrate is connected, with its first main surface, to the first main surface of the second substrate so that the RF elements project into the at least one cavity.

A transistor is disclosed having a substrate, a device layer disposed over the substrate, a gate electrode disposed over the device layer, and a drain electrode disposed over the substrate and spaced from the gate electrode. A first source electrode is disposed over the substrate opposite the drain electrode and spaced from the gate electrode. A second source electrode is disposed over the substrate spaced from the drain electrode opposite the gate electrode. A dielectric is disposed over the device layer, the gate electrode, and the drain electrode between the first source electrode and the second source electrode. A conductive interconnect couples the first source electrode and the second electrode and extends over the dielectric. The conductive interconnect comprises a shield wall that extends from the conductive interconnect into the dielectric between the gate electrode and the drain electrode with a distal end that is spaced above the device layer.