A liquid circulating cooling package substrate includes a circulating cooling structure including a cooling chamber in a first dielectric layer to expose a heat dissipation face, a metal heat dissipation layer on the inner surface of the cooling chamber, an upright support column formed on a metal heat dissipation layer, and a cooling cover supported on the support column to close the cooling chamber along the periphery of the cooling chamber. The metal heat dissipation layer completely covers the heat dissipation face and the inner side surface of the cooling chamber, and a liquid inlet and a liquid outlet are formed on the cooling cover. A circulating cooling structure is provided in the first dielectric layer, and the circulating cooling structure is formed during the processing of an embedded package substrate such that the processing flow is simple and the cost is low.

A transistor includes a semiconductor die with an active region and one or more non-active regions that do not overlap or overlie the active region. The transistor further includes a group of multiple transistor fingers in the active region. One or more source vias are located adjacent to sides of the group of transistor fingers. One or more source manifolds are located in the non-active region(s), and the source manifold(s) electrically connect the source via(s) with at least one source region of the multiple transistor fingers.

An assembly includes a passive component embodied as a shunt resistor, and a first substrate including a first conductor track and a second conductor track, with the first conductor track being electrically conductively connected to the second conductor track by way of the passive component. The first substrate includes a cavity or an opening into which the passive component protrudes. A second substrate is electrically conductively connected to the first substrate by way of the passive component and includes a dielectric material layer. A heat sink is arranged on a side of the second substrate facing away from the first substrate and is connected to the passive component in an electrically insulating and thermally conductive manner by way of the dielectric material layer of the second substrate. The passive component is arranged on a side of the second substrate facing toward the first substrate.

An assembly includes a passive component embodied as a shunt resistor, and a first substrate including a first conductor track and a second conductor track, with the first conductor track being electrically conductively connected to the second conductor track by way of the passive component. The first substrate includes a cavity or an opening into which the passive component protrudes. A second substrate is electrically conductively connected to the first substrate by way of the passive component and includes a dielectric material layer. A heat sink is arranged on a side of the second substrate facing away from the first substrate and is connected to the passive component in an electrically insulating and thermally conductive manner by way of the dielectric material layer of the second substrate. The passive component is arranged on a side of the second substrate facing toward the first substrate.

A method for making a recess or opening in a planar workpiece with a thickness of less than 3 millimeters includes successively etching a plurality of flaws to form the recess or opening such that a contour of the recess or opening has a sequence of widenings and constrictions as a result of the etching.

Disclosed is a semiconductor package device comprising a lower redistribution substrate, a first semiconductor chip on the lower redistribution substrate, vertical structures on the lower redistribution substrate, and a first molding member on the lower redistribution substrate and on the first semiconductor chip and the vertical structures. The vertical structure includes a first post having a first diameter, a second post on the first post and having a second diameter, and a bonding pad on the second post opposite the first post and having a third diameter. The first, second, and third diameters are different from each other. The third diameter is greater than the second diameter.

A semiconductor composite device is provided that includes a voltage regulator including a plurality of active elements and a plurality of passive elements and arranged with a plurality of channels; a load including a semiconductor element and that is supplied with a direct-current voltage and regulated by the voltage regulator; and a wiring board electrically connected to the plurality of active elements, the plurality of passive elements, and the load. The load is disposed on a first mounting surface of the wiring board, and the first and second inductors are disposed on a second mounting surface of the wiring board that is opposite the first mounting surface. The first inductor is electrically connected to the wiring board via a first capacitor, and the second inductor is electrically connected to the wiring board via a second capacitor.

A wiring board according to the present disclosure includes: a first insulation layer having a first surface; a land conductor located on the first surface; a second insulation layer covering the first surface and the land conductor and having a second surface on a side opposite to the first insulation layer; a via hole penetrating from the second surface of the second insulation layer to the land conductor; and a via hole conductor located in the via hole and in contact with the land conductor. The via hole conductor includes an underlying metal layer and an electrolytic plating layer located on the underlying metal layer, the underlying metal layer being located on a surface of the land conductor, a wall surface of the via hole, and the second surface. A plurality of voids are located in at least a portion of the underlying metal layer.

A wiring board according to the present disclosure includes: a first insulation layer having a first surface; a land conductor located on the first surface; a second insulation layer covering the first surface and the land conductor and having a second surface on a side opposite to the first insulation layer; a via hole penetrating from the second surface of the second insulation layer to the land conductor; and a via hole conductor located in the via hole and in contact with the land conductor. The via hole conductor includes an underlying metal layer and an electrolytic plating layer located on the underlying metal layer, the underlying metal layer being located on a surface of the land conductor, a wall surface of the via hole, and the second surface. A plurality of voids are located in at least a portion of the underlying metal layer.

Disclosed herein are microelectronics package architectures utilizing glass layers and methods of manufacturing the same. The microelectronics packages may include a silicon layer, dies, and a glass layer. The silicon layer may include vias. The dies may be in electrical communication with vias. The glass layer may include interconnects in electrical communication with the vias.