A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity on the conductive via structure.

Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

A package structure is provided. The package structure includes a first interconnect structure formed over a first substrate. The package structure also includes a second interconnect structure formed below a second substrate. The package structure further includes a bonding structure between the first interconnect structure and the second interconnect structure. In addition, the bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC). The bonding structure also includes an underfill layer surrounding the bonding structure. A width of the first IMC is greater than a width of the second IMC, and the underfill layer covers a sidewall of the first IMC and a sidewall of the second IMC.

A method of forming a semiconductor device includes providing a substrate having a patterned film including manganese; depositing a graphene layer over exposed surfaces of the patterned film; depositing a dielectric layer containing silicon and oxygen over the graphene layer; and heat-treating the substrate to form a manganese-containing diffusion barrier region between the graphene layer and the dielectric layer.

Methods and apparatus for transient protection of a sensitive surface of a substrate are described. Methods that facilitate transient protection of a sensitive surface of substrate include depositing a sacrificial capping layer on a sensitive surface of the substrate after a processing operation. The capping layer deposition and the prior processing operation occur under vacuum. In some embodiments, for example, the capping layer deposition and the prior processing operation occur in different modules of a tool connected by a vacuum transfer chamber. In other embodiments, the capping layer deposition and the prior processing operation occur in the same module Methods that facilitate transient protection of a sensitive surface of substrate include removing the capping layer from the sensitive surface of the substrate prior to a subsequent processing operation. The removal is performed without damaging the sensitive surface or underlying layers of the semiconductor substrate.

An integrated circuit structure includes a first interconnect layer including a first dielectric material. The first dielectric material has a first recess therein, the first recess having a first opening. The integrated circuit structure further includes a second interconnect layer above the first interconnect layer. The second interconnect layer includes a second dielectric material that has a second recess therein. The second recess has a second opening. In an example, at least a portion of the first opening of the first recess abuts and overlaps with at least a portion of the second opening of the second recess. In an example, a continuous conformal layer is on walls of the first and second recesses, and a continuous body of conductive material is within the first and second recesses.

Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner/film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and/or zinc silicon oxide (ZnSiO.sub.x) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance/capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.

Conditions at the perimeter of the wafer may be characterized and used to adjust current stolen by the weir thief electrodes during a plating process to generate more uniform film thicknesses. An electrode may be positioned in a plating chamber near the periphery of the wafer as the wafer rotates. To characterize the electrical contacts on the seal, a wafer with a seed layer may be loaded into the plating chamber, and a constant current may be driven through the electrode into the conductive layer on the wafer. As an electrical characteristic of this current varies, such as a voltage required to drive a constant current, a mapping characterizing the seal quality or the openings in the mask layer may be generated.

A method of manufacturing a semiconductor package includes forming a plurality of redistribution pads including a first pad layer, a second pad layer, and a third pad layer sequentially stacked on a redistribution structure, forming a preliminary seed layer conformally extending on an upper surface of the redistribution structure, and on upper surfaces and side surfaces of the plurality of redistribution pads, forming a metal pillar on the preliminary seed layer, forming surface roughness on the metal pillar, and etching at least a portion of the preliminary seed layer exposed on the side surfaces of the plurality of redistribution pads and the upper surface of the redistribution structure to provide a seed layer between the metal pillar and one of the plurality of redistribution pads thereon.

A described example includes a method for fabricating an integrated circuit (IC) device. The method includes forming a barrier layer over a surface of a semiconductor substrate and a conductive terminal in the surface. The method also includes forming a conductive seed layer over the barrier layer and at least a portion of the surface of the semiconductor substrate. The method also includes forming a conductive post over the seed layer, in which the conductive post includes a sidewall portion extending from a proximal end at the seed layer to terminate in a distal end spaced apart from the seed layer. The method also includes forming a passivation layer over the surface of the semiconductor substrate and surrounding the sidewall portion of the conductive post.