Exemplary semiconductor structures may include a substrate defining a device layer. The structures may include a first deep-trench-capacitor (DTC) coupled to a first surface of the substrate. The structures may include a second DTC coupled to a second surface of the substrate opposite the first surface of the substrate.

A method includes: forming a first oxide layer having a thickness of 400 nm or less on a first main surface of a semiconductor wafer; forming a second layer on the first oxide layer; altering an etch rate of at least a first part of the second layer such that a horizontal component (r1) of the etch rate is greater than a vertical component (r2) of an etch rate of the first oxide layer; etching the oxide layers through an opening in a mask using an isotropic etchant, wherein due to the difference between r1 and r2, a first thickness transition region of the first oxide layer under the mask is etched with a taper of less than 45 degrees relative to the first main surface; after the etching, removing the second layer and then forming a gate oxide adjacent to the first thickness transition region.

Embodiments of present invention provide a semiconductor structure. The structure includes a metal via having a substantially hyperboloid exterior shape; and a dielectric layer surrounding the metal via, where the metal via includes a bottom portion and a top portion; the top portion includes an outer liner and an inner liner at sidewalls thereof; and the bottom portion is directly surrounded by the dielectric layer. A method of forming the same is also provided.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

A power chip package structure includes a power chip, a first transmission member, and at least two second transmission members, an encapsulant, and a diamond-like carbon (DLC) layer. The first transmission member and the at least two second transmission members are connected to the power chip. The power chip, the first transmission member, and the at least two second transmission members are embedded in the encapsulant. The encapsulant has a layout surface that is coplanar with a first end surface of the first transmission member and a second end surface of each of the at least two second transmission members. The DLC layer is formed on the layout surface with terminals. The DLC layer surrounds the first end surface to jointly form a first solder-receiving slot, and the DLC layer surrounds each of the two second end surfaces to jointly form a second solder-receiving slot.

A surface mount component is disclosed including an electrically insulating beam that is thermally conductive. The electrically insulating beam has a first end and a second end that is opposite the first end. The surface mount component includes a thin-film component formed on the electrically insulating beam adjacent the first end of the electrically insulating beam. A heat sink terminal is formed on the electrically insulating beam adjacent a second end of the electrically insulating beam. In some embodiments, the thin-film component has an area power capacity of greater than about 0.17 W/mm.sup.2 at about 28 GHz.

An apparatus includes an interposer configured to be electrically coupled to one or more semiconductor devices. The interposer includes a core having a substrate and first vias through the substrate, a first stackup of layers over a first side of the core, and a second stackup of layers over a second side of the core. The first stackup of layers includes first redistribution layers and first dielectric layers. The first redistribution layers are electrically coupled together using second vias through the first dielectric layers, and the first stackup of layers forms a first and a second stripline. The second stackup of layers includes second redistribution layers and second dielectric layers. The second redistribution layers are electrically coupled together using third vias through the second dielectric layers, and the second stackup of layers forms a third stripline.

An apparatus and method for manufacturing a power module is provided. The power module includes: a circuit board having a metal pattern formed thereon; a terminal coupled to the circuit board and electrically connected to at least a portion of the metal pattern; a power device chip bonded to the circuit board and electrically connected to at least a portion of the metal pattern and the terminal; and a molding part covering the power device chip and the circuit board. The circuit board includes: a base part comprising an insulating material; a pattern layer disposed on at least one of an upper surface and a lower surface of the base part and providing the metal pattern; and a thin film resistor having a predetermined circuit pattern connecting the metal patterns disposed on the base part to each other.

An assembly includes a passive component embodied as a shunt resistor, and a first substrate including a first conductor track and a second conductor track, with the first conductor track being electrically conductively connected to the second conductor track by way of the passive component. The first substrate includes a cavity or an opening into which the passive component protrudes. A second substrate is electrically conductively connected to the first substrate by way of the passive component and includes a dielectric material layer. A heat sink is arranged on a side of the second substrate facing away from the first substrate and is connected to the passive component in an electrically insulating and thermally conductive manner by way of the dielectric material layer of the second substrate. The passive component is arranged on a side of the second substrate facing toward the first substrate.

Some embodiments relate to an integrated device, including: a resistor and capacitor structure coupled in series between a high voltage wire and a low voltage wire, the resistor and capacitor structure having a first node electrically coupled to a resistor and a capacitor; a transistor comprising a first source/drain terminal coupled to the high voltage wire, a second source/drain terminal coupled to the low voltage wire, and a gate terminal; and a diode coupled between the gate terminal and either the high voltage wire or the low voltage wire.