A middle voltage transistor with a fin structure includes a substrate. A fin structure protrudes from a surface of the substrate. A gate structure crosses the fin structure. A source is disposed at one side of the gate structure and embedded in the fin structure, and a drain is disposed at the other side of the gate structure and embedded in the fin structure. A second deep trench isolation is embedded in the substrate and adjacent to the source and drain. An isolation structure is embedded in the fin structure below the gate structure. The isolation structure includes a first deep trench isolation and a first shallow trench isolation extending from a sidewall of the first deep trench isolation toward the source.

For manufacturing a memory device, a system may form a trench between a first portion and a second portion of a stack. A bottom wall of the trench may include a spacer material. The system may remove a first and a second oxide material to reform the trench, and remove a polysilicon material in a lateral direction to expose a third oxide material and a channel structure. The third oxide material may form the bottom wall of the trench. The system may remove, in a lateral direction, the first oxide material, a portion of the second oxide material, the third oxide material, and a fourth oxide material of the channel structure. The system may deposit a metal material, in the trench, in contact with a doped polysilicon material of the channel structure.

The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

An LDMOS includes a semiconductor substrate. The semiconductor substrate includes a fin structure and a planar substrate. The fin structure extends from the planar substrate. A gate electrode covers the planar substrate and the fin structure. A first gate dielectric layer is disposed between the gate electrode and the planar substrate. A second gate dielectric layer is between the gate electrode and the fin structure and between the gate electrode and the planar substrate. The first gate dielectric layer is connected to the second gate dielectric layer. A source is disposed in the fin structure at one side of the gate electrode and a drain is disposed in the planar structure at the other side of the gate electrode.

A semiconductor device fabrication method includes forming a substrate having first and second regions therein, with different densities of active regions in the first and second regions. A cell trench is formed, which defines cell active regions in the first region, and a peripheral trench is formed, which defines peripheral active regions in the second region. A first insulating layer is formed in the cell trench and the peripheral trench. A mask is selectively formed, which covers the first insulating layer in the first region and exposes the first insulating layer in the second region. A second insulating layer is formed on the first insulating layer in the second region exposed by the mask, using a selective dielectric-on-dielectric deposition process. The first insulating layer is exposed in the first region by removing the mask. A third insulating layer is formed on the first insulating layer in the first region and on the second insulating layer in the second region.

A semiconductor structure manufacturing method includes: providing a substrate and etching the substrate to form first trenches; filling each of the first trenches with an oxide layer having a top surface not lower than that of the substrate; etching regions, adjacent to side walls of the first trench, in the oxide layer downwards to form second trenches, wherein a depth of the second trench is less than a depth of the first trench and a width of the second trench is less than half of a width of the first trench; and forming supplementary layers in the second trenches.

Techniques are provided herein to form semiconductor devices that include gate cuts with different widths (e.g., at least a 1.5 difference in width) but substantially the same height (e.g., less than 5 nm difference in height). A given gate structure extending over one or more semiconductor regions may be interrupted with any number of gate cuts that each extend through an entire thickness of the gate structure. According to some embodiments, gate cuts of a similar first width are formed via a first etching process while gate cuts of a similar second width that is greater than the first width are formed via a second etching process that is different from the first etching process. Using different etch processes for gate cuts of different widths maintains a similar height for the gate cuts of different widths.

A semiconductor trench capacitor structure is provided. The semiconductor trench capacitor comprises a semiconductor substrate; a trench capacitor overlying the semiconductor substrate, wherein the trench capacitor comprises a plurality of trench electrodes and a plurality of capacitor dielectric layers that are alternatingly stacked over the semiconductor substrate and defines a plurality of trench segments and a plurality of pillar segments, wherein the trench electrodes and the capacitor dielectric layers are recessed into the semiconductor substrate at the trench segments, and wherein the trench segments are separated from each other by the pillar segments; and a protection dielectric layer disposed between the semiconductor substrate and the trench capacitor, wherein the protection dielectric layer has a thickness greater than thicknesses of the trench electrodes.