H10W72/322

FLIP CHIP LIGHT EMITTING DIODE (LED) INTERCONNECT
20260018553 · 2026-01-15 ·

Disclosed embodiments provide light-emitting diodes (LEDs) and interconnect structures that employ particularly shaped electrodes and a conductive metal-based adhesive that are selected to provide a flexible, robust interconnect that is capable of resisting lateral shear forces, while maintaining a low bond process temperature that is process compatible with other LED component materials. In a non-limiting aspect, disclosed embodiments employ a barrier coating on the interconnect or bonding materials comprising a conductive metal-based adhesive to inhibit moisture and air contact with the conductive metal-based adhesive, thereby preventing or mitigating migration of metal ions in the conductive metal-based adhesive in operation.

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a plurality of first wafers and a through-substrate via (TSV). The plurality of first wafers include a plurality of conductive connection lines. Each of the conductive connection lines is located in the corresponding first wafer. The through-substrate via passes through the plurality of first wafers and a plurality of end portions of the plurality of conductive connection lines. The plurality of end portions are embedded in the through-substrate via.

THERMALLY CONDUCTIVE SUBSTRATE BONDING INTERFACE
20260027805 · 2026-01-29 ·

A bonded substrate structure includes a first substrate; a second substrate; and a bonding region bonding the first substrate to the second substrate. The bonding region includes an aluminum oxide bonding layer directly contacting an aluminum nitride layer, and a bonding interface between the aluminum oxide bonding layer and a bonding surface of the first substrate or the second substrate.

ELECTRONIC DEVICE HAVING SUBSTRATE CAVITIES FOR POSITIONING ELECTRONIC UNITS AND MANUFACTURING METHOD THEREOF
20260060121 · 2026-02-26 · ·

An electronic device includes a substrate, a through hole, a first electronic unit, a second electronic unit, a circuit structure, and a third electronic unit. The substrate has a first surface, a second surface opposite the first surface, a first cavity, and a second cavity. A sidewall of the first cavity is connected to the first surface, and a sidewall of the second cavity is connected to the first surface. The through hole extends through the substrate, and a sidewall of the through hole is connected to the first surface and the second surface. The first electronic unit is disposed in the first cavity. The second electronic unit is disposed in the second cavity. The circuit structure is disposed on the first electronic unit and the second electronic unit. The bottom surfaces of the first and second cavities have a roughness ranging from 0 to 2 micrometers.

SUBSTRATE ARRANGEMENT, METHOD FOR PRODUCING AN ELECTRONIC ASSEMBLY, AND ELECTRONIC ASSEMBLY
20260060125 · 2026-02-26 ·

The invention relates to a substrate arrangement, to a method for producing an electronic assembly and to an electronic assembly. The substrate arrangement comprises (a) a metal foil comprising an upper side and an underside, (b) a silver layer arranged on the underside of the metal foil, and (c) a silver sinter layer arranged on the silver layer, wherein the silver layer has a thickness d(Ag) in the range of 20-1500 nm.

Semiconductor Device and Connecting Method
20260060098 · 2026-02-26 ·

The purpose of this invention is to provide a semiconductor device that prevents defects in semiconductor elements caused by differences in thermal expansion and maintains low electrical resistance by directly or indirectly laminating an FeNi alloy metal layer onto the front-surface or back-surface electrodes of the semiconductor element. In this invention, an FeNi alloy metal layer is directly or indirectly applied on the surface electrodes of the semiconductor element, and the semiconductor element is connected to a conductor through the FeNi alloy metal layer. Depending on the application, the Ni content of the FeNi alloy metal layer is set within the range of 36% to 45% by weight, and the thickness of the FeNi alloy metal layer is set within the range of 2 m to 20 m.

WAFER-TO-WAFER BONDING STRUCTURE AND FABRICATION METHOD THEREOF

A wafer-to-wafer bonding structure includes a first wafer having a first bonding layer thereon, a first main pattern region, a first scribe lane surrounding the first main pattern region, and a first alignment cavity disposed in the first bonding layer within the first main pattern region; and a second wafer having a second bonding layer bonded to the first bonding layer, a second main pattern region, a second scribe lane surrounding the second main pattern region, and a second alignment cavity disposed in the second bonding layer within the second main pattern region.

DIE ATTACH FILM STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
20260047392 · 2026-02-12 ·

A die attach film structure includes a dicing film, an insulating adhesion layer including an upper surface and a lower surface opposite the upper surface, the lower surface of the insulating adhesion layer contacting an upper surface of the dicing film and including an insulating filler, and a conductive adhesion layer contacting an upper surface of the insulating adhesion layer and including a conductive filler.

3D CHIPLET INTEGRATION TECHNOLOGY
20260047484 · 2026-02-12 ·

An exemplary interconnect structure includes a first substrate, a second substrate vertically below the first substrate; and an underlayer structure between and in contact with the first and second substrates in which the underlayer structure between and in contact with the first and second substrates, a conductive connector between and electrically connecting the first and second substrates. The underlayer structure comprises an electromagnetic curable layer and a high thermal conductive layer and the underlayer structure laterally surrounds the conductive connector.

WAFER BONDING WITH ENHANCED THERMAL DISSIPATION

The present disclosure describes a bonded semiconductor structure and a method of forming the bonded semiconductor structure. The bonded semiconductor structure includes first and second substrates bonded with a bonding structure. The bonding structure provides high thermal conductivity and high bonding strength between the first and second substrates. The bonding structure includes bonding layers and adhesion layers, with the bonding layers including titanium oxide and the adhesion layers including titanium nitride. The method includes forming a first adhesion layer on the first substrate and a second adhesion layer on the second substrate. The method also includes forming a first bonding layer on the first adhesion layer and a second bonding layer on the second adhesion layer. The method further includes bonding the first and second substrates by bonding the first and second bonding layers together.