Provided is a semiconductor package including a first semiconductor chip, an inter-chip die on the first semiconductor chip in a first direction perpendicular to an upper surface of the first semiconductor chip, and a second semiconductor chip on the inter-chip die in the first direction, and the inter-chip die includes a first surface configured to face the first semiconductor chip, a second surface configured to face the second semiconductor chip, and a trench at least partially defined by the inter-chip die, the trench recessed in the first surface toward the second surface.

A region of a sealing part is effectively utilized. A semiconductor device includes a semiconductor element, a substrate, a sealing part, and a cavity region. The substrate included in this semiconductor device is disposed adjacent to a bottom surface of the semiconductor element. The sealing part included in this semiconductor device is formed in a shape that covers an upper surface that is a surface facing the bottom surface of the semiconductor element, and seals the semiconductor element. The cavity region included in this semiconductor device is a region disposed in the sealing part and formed with a cavity.

Electronic module (1) including an encapsulation (20), a carrier substrate (10) enclosed by the encapsulation (20) and having a component side (25) which has a first metallization layer (15) and on which at least one first electronic component (30) is arranged, wherein at least one second metallization layer (35) for at least one second electronic component (31), in particular for controlling the first electronic component (30), is provided on an outer side (A) of the encapsulation (2), wherein the encapsulation (20) has at least one plated-through hole (5) for electrical connection, in particular for direct electrical connection, of the first electronic component (30) and the second electronic component (31).

The present disclosure relates to packaging techniques in connection with packaging electrical and optical components within circuit packages. For example, one or more examples described herein involve producing or manufacturing wafers having circuit packages formed thereon. Techniques described herein related to modifying a dimension of wafers in order that the wafers conform to a nominal dimension, such that the wafers may be implemented in connection with processing equipment that is specifically configured to operate on wafers of the nominal dimension.

In an embodiment, a package includes an encapsulant laterally surrounding a first integrated circuit device and a second integrated circuit device, wherein the first integrated circuit device includes a die and a heat dissipation structure over the die; a sealant disposed over the heat dissipation structure; an adhesive disposed over the second integrated circuit device; and a lid disposed over the sealant and the adhesive, wherein the lid includes a first cooling passage and a second cooling passage, the first cooling passage including an opening at a bottom of the lid and aligned to the heat dissipation structure, the second cooling passage including channels aligned to the second integrated circuit device and being distant from the bottom of the lid.

A semiconductor device, including: a semiconductor chip including an upper surface electrode and a lower surface electrode; an insulated circuit board having on an upper surface thereof a conductive circuit pattern layer, on which the lower surface electrode is disposed; a wiring board having on a lower surface thereof a wiring pattern layer, which faces the upper surface of the insulated circuit board, and is electrically connected to the upper surface electrode; a conductive spacer disposed between the conductive circuit pattern layer and the wiring pattern layer, and having: a lower bonding surface and an upper bonding surface respectively bonded to the conductive circuit pattern layer and the wiring pattern layer; and an encapsulating member encapsulating the semiconductor chip, the insulated circuit board, the wiring board and the conductive spacer while exposing the upper bonding surface of the conductive spacer and a lower surface of the insulated circuit board.

A hybrid integrated heat spreader suitable for an integrated circuit (IC) die package. The hybrid integrated heat spreader includes a top sheet material and a sealant interface material located where the heat spreader is to contact an assembly substrate. The sealant interface material may offer greater adhesion to a sealant employed between the interface material and the package substrate. In some examples, the sealant interface material has a greater surface roughness and/or a different composition than a surface of the integrated heat spreader that is in close thermal contact with an IC die through a thermal interface material. With the sealant interface material improving adhesion, the sealant may have a higher bulk modulus, enabling the integrated heat spreader to impart greater stiffness to the IC die package assembly.

The present invention provides a photonic device, comprising a photonic integrated circuit including a waveguide structure having a core layer and a cladding layer surrounding the core layer, a first cavity formed through a top surface of the photonic integrated circuit and at least partly into the cladding layer, an adhesive layer formed on at least a first surface of the first cavity, and a first photonic element arranged in the first cavity and bonded to the adhesive layer on the first surface of the first cavity, wherein at least a portion of the cladding layer and a portion of the adhesive layer define a first coupling region configured to enable coupling of an optical mode between the core layer and the first photonic element through the coupling region. Further the present invention provides a corresponding method for manufacturing a photonic device as well as.

A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.