A method of forming a semiconductor structure includes forming a photoresist over a first conductive pattern. The method further includes patterning the photoresist to define a plurality of first openings. The method further includes depositing a conductive material in each of the plurality of first openings. The method further includes disposing a molding material over the first conductive pattern, wherein the molding material surrounds a die. The method further includes removing a portion of the molding material to form a second opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a redistribution structure over the molding material and the dielectric member, wherein the redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.

A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

A semiconductor device manufacturing method includes forming a first film containing a first device on a first substrate, forming a second film containing a semiconductor layer on a second substrate, and changing the semiconductor layer into a porous layer. The method further includes forming a third film containing a second device on the second film, and bonding the first substrate and the second substrate to sandwich the first film, the third film, and the second film therebetween. The method further includes separating the first substrate and the second substrate from each other at a position of the second film.

A method for making an electronic package is provided. The method includes providing a substrate strip comprising substrate assemblies, each substrate assembly comprises a first substrate and a second substrate connected to the first substrate via a flexible link, the first substrate comprises a first mounting surface, the second substrate comprises a second mounting surface that is not at a same side of the substrate assembly as the first mounting surface; disposing the substrate strip on a first carrier; attaching a first electronic component onto the first mounting surface; disposing the substrate strip on a second carrier with a plurality of cavities, the first electronic component is received within one of the plurality of cavities; attaching a second electronic component onto the second mounting surface; singulating the substrate assemblies from each other; and bending the flexible link to form an angle between the first substrate and the second substrate.

In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

In one example, a semiconductor device comprises a first substrate comprising a first conductive structure, a first body over the first conductive structure and comprising an inner sidewall defining a cavity in the first body, a first interface dielectric over the first body, and a first internal interconnect in the first body and the first interface dielectric, and coupled with the first conductive structure. The semiconductor device further comprises a second substrate over the first substrate and comprising a second interface dielectric, a second body over the second interface dielectric, and a second conductive structure over the second body and comprising a second internal interconnect in the second body and the second interface dielectric. An electronic component is in the cavity, and the second internal interconnect is coupled with the first internal interconnect. Other examples and related methods are also disclosed herein.

A semiconductor package includes a lower interconnect structure. The lower interconnect structure includes a lower insulating layer and lower interconnect patterns. A first encapsulation layer is disposed on the lower interconnect structure. A pillar electrode penetrating the first encapsulation layer and connected to the lower interconnect patterns is provided. An upper interconnect structure disposed within the first encapsulation layer and having an upper insulating layer and upper interconnect patterns is provided. A distance between an upper surface of the lower interconnect structure and an uppermost end of the first encapsulation layer is larger than a distance between the upper surface of the lower interconnect structure and an uppermost end of the upper interconnect structure. A second encapsulation layer is disposed on the first encapsulation layer. A semiconductor chip disposed within the second encapsulation layer and connected to the pillar electrode and upper interconnect patterns is provided.