Patent classifications
H10W10/30
Silicon carbide power device with integrated resistance and corresponding manufacturing process
A silicon carbide power device has: a die having a functional layer of silicon carbide and an edge area and an active area, surrounded by the edge area; gate structures formed on a top surface of the functional layer in the active area; and a gate contact pad for biasing the gate structures. The device also has an integrated resistor having a doped region, of a first conductivity type, arranged at the front surface of the functional layer in the edge area; wherein the integrated resistor defines an insulated resistance in the functional layer, interposed between the gate structures and the gate contact pad.
Silicon carbide MOSFET transistor device with improved characteristics and corresponding manufacturing process
A MOSFET transistor device includes a functional layer of silicon carbide, having a first conductivity type. Gate structures are formed on a top surface of the functional layer and each includes a dielectric region and an electrode region. Body wells having a second conductivity type are formed within the functional layer, and the body wells are separated from one another by surface-separation regions. Source regions having the first conductivity type are formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.
SEMICONDUCTOR DEVICE WITH IMPROVED BREAKDOWN VOLTAGE AND ASSOCIATED MANUFACTURING METHOD
A method for forming a semiconductor device having a tub. The method includes forming a substrate of a first conductivity type that includes a tub bottom layer of the tub. The tub bottom layer is of a second conductivity type that is opposite to the first conductivity type and has a tub bottom layer peak dopant concentration plane that is substantially away from a top surface of an initial substrate layer of the substrate for a predetermined tub bottom layer buried depth that is essentially greater than 0.5 m. The method can further include forming a plurality of tub sidewalls of the tub. The method can further include forming a high voltage transistor inside the tub.