The present disclosure provides a packaging device and a method to form the packaging device. The packaging device includes a package base, a die structure disposed over the package base, and a package lid over the die structure. The package lid is thermally coupled with the die structure and the package base.

In one example, an electronic device comprises a substrate comprising a conductive structure and an inner side and an outer side, a first electronic component over the inner side of the substrate and coupled with the conductive structure, a lid over the substrate and the first electronic component and comprising a first hole in the lid, and a thermal interface material between the first electronic component and the lid. The thermal interface material is in the first hole. Other examples and related methods are also disclosed herein.

A package structure is provided. The package structure includes a substrate including a cavity and a plurality of thermal vias connecting a bottom surface of the cavity to a bottom surface of the substrate. The package structure also includes an electronic device disposed in the cavity and thermally coupled to the plurality of thermal vias. The package structure further includes a plurality of conductive connectors formed over the electronic device and vertically overlapping the plurality of thermal vias. The package structure also includes an encapsulating material extending from top surfaces of the plurality of conductive connectors to the bottom surface of the cavity. The package structure further includes an insulating layer formed over the encapsulating material and including a redistribution layer structure electrically connected to the electronic device through the plurality of conductive connectors.

A high-density integrated device package may include two or more primary device dies arranged along a first plane, an inductor comprising an inductor core and an inductor coil, the inductor being fixedly connected to at least one of the primary device dies, and a dielectric substrate arranged along a second plane which is substantially perpendicular to the first plane. The integrated device package further includes a secondary device die (e.g., a power IC) electrically connected to the dielectric substrate such that an orientation of the secondary device die is substantially perpendicular to that of the two or more primary device dies, wherein the dielectric substrate is fixedly connected to the inductor core, and wherein the dielectric substrate is electrically connected to at least one of the primary device dies by an edge connector.

The present disclosure in general relates to the field of heat sinks (e.g. microchannel heat sinks). The present disclosure is further directed towards a microchannel heat sink for applications in microchips. The microchannel heat sink comprises a base and a plurality of microchannel units extending from the base. The plurality of microchannel units are arranged in parallel and at regular intervals on the base. Each microchannel unit comprises two or more pin-fins. Each pin-fin comprises a triply periodic minimal surface (TPMS) lattice structure. The present disclosure also relates to pin-fins comprising triply periodic minimal surface (TPMS) lattice structure.

A chip package structure includes an assembly containing an interposer and semiconductor dies; a packaging substrate attached to the assembly through solder material portions; and a lid structure attached to the packaging substrate. The lid structure includes: a first plate portion having a first thickness and located in an interposer-projection region having an areal overlap with the interposer in a plan view; a second plate portion having a second thickness that is less than the first thickness, laterally surrounding, and adjoined to, the first plate portion, and located outside the interposer-projection region; and a plurality of foot portions adjoined to the second plate portion, laterally spaced from the first plate portion, and attached to a respective top surface segment of the packaging substrate through a respective adhesive portion.

A thermal substrate includes a multilayer film, a first conductive layer adhered to the first outer layer of the multilayer film and a second conductive layer adhered to the second outer layer of the multilayer film. The multilayer film includes a first outer layer including a first thermoplastic polyimide, a core layer including a polyimide and a second outer layer including a second thermoplastic polyimide. The multilayer film has a total thickness in a range of from 5 to 150 m, and the first outer layer, the core layer and the second outer layer each include a thermally conductive filler. The first conductive layer and the second conductive layer each have a thickness in a range of from 250 to 3000 m.

Chip packages, electronic devices and method for making the same are described herein. The chip packages and electronic devices have a heat spreader disposed over a plurality of integrated circuit (IC) devices. The heat spreader has an opening through which a protrusion from an overlaying cover extends into contact with one or more of the IC devices to provide a direct heat transfer path to the cover. Another one or more other IC devices have a heat transfer path to the cover through the heat spreader. The separate heat transfer paths allow more effective thermal management of the IC devices of the chip package.

A thermal dissipation system for an integrated circuit (IC) includes an IC disposed on a substrate and a heat sink including a body having a first surface including a first part coupled to a side of the IC opposite the substrate and a second part disposed away from the IC and positioned in spaced relation to the substrate. A set of legs support at least the second part of the body in spaced relation to the substrate. The set of legs may be part of the body or may be part of a carrier disposed between the second part of the first surface of the body and the substrate. The carrier includes an opening through which a portion of the substrate that includes the first part that is coupled to the side of the IC opposite the substrate extends.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.