An example semiconductor package includes a substrate, a semiconductor chip on the substrate, a heat-dissipation structure on the substrate, heat transfer paste, and a molding layer covering the heat transfer paste. The heat-dissipation structure is horizontally apart from the semiconductor chip. The heat transfer paste is between the semiconductor chip and the heat-dissipation structure. A top surface of the heat transfer paste is at a lower vertical level than a top surface of the heat-dissipation structure.

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

A packaged chip and a method for manufacturing the packaged chip are provided. The packaged chip includes a substrate, a chip, and a heat sink. The heat sink includes a first bracket, a second bracket, and a cover. The first bracket and the second bracket are disposed on the substrate. The cover is supported on the substrate by the first bracket and the second bracket. The first bracket is a sealed annular bracket. The first bracket and the cover encircle a first space. The chip is accommodated in the first space. A thermal interface material is disposed between the chip and the cover. A hole connected to the first space is provided on the cover. The hole and the first space are filled with a filling material. The second bracket is located outside the first space.

Provided is a thermosetting resin composition containing: (A) silver particles including secondary particles having an average particle size from 0.5 to 5.0 m, the secondary particles being formed by aggregation of primary particles having an average particle size from 10 to 100 nm; and (B) a thermosetting resin.

Provided is a semiconductor package including a package substrate, a first semiconductor device arranged on the package substrate, a second semiconductor device arranged on the first semiconductor device, a heat dissipation structure arranged on the second semiconductor device, and at least one first chip stack including a plurality of first core chips apart from the first semiconductor device in a lateral direction and sequentially stacked on the package substrate and a first buffer chip arranged on the second semiconductor device and the plurality of first core chips, wherein the heat dissipation structure is arranged apart from the first buffer chip in the lateral direction, and the plurality of first core chips include a plurality of first core through electrodes configured to penetrate at least a portion of each of the plurality of first core chips.

Provided are silver particles including a silver powder and a silver layer that includes primary particles, the primary particles being smaller than the silver powder.

An apparatus is described. The apparatus includes a metallic chamber having a first outer surface with first Peltier devices and a second outer surface with second Peltier devices. The first and second outer surfaces face in opposite directions such that the first Peltier devices are to cool first semiconductor chips that face the first outer surface and the second Peltier devices are to cool second semiconductor chips that face the second outer surface.

Semiconductor devices including the use of solder materials and methods of manufacturing are provided. In embodiments the solder materials utilize a first tensile raising material, a second tensile raising material, and a eutectic modifier material. By utilizing the materials a solder material can be formed and used with a reduced presence of needles that may otherwise form during the placement and use of the solder material.

A cooling package for an integrated circuit, including: package substrate of the integrated circuit having a first package surface, an enclosure and a thermal conductive material filling a gap between the substrate and a circuit die locatable therein and filling a gap between interior sidewalls of the enclosure and sidewall surfaces of the circuit die couplable to the first package surface. A method including: mounting an enclosure to the first package surface, the enclosure surrounding a location on the first package surface the circuit die is couplable thereto and the circuit die is locatable therein, and, filling the enclosure with the thermal conductive material such that the gaps are filled with the thermal conductive material. An integrated circuit cooling package including the substrate, first and second enclosures and first and second thermal conductive materials is also disclosed.