A cooling package for an integrated circuit, including: package substrate of the integrated circuit having a first package surface, an enclosure and a thermal conductive material filling a gap between the substrate and a circuit die locatable therein and filling a gap between interior sidewalls of the enclosure and sidewall surfaces of the circuit die couplable to the first package surface. A method including: mounting an enclosure to the first package surface, the enclosure surrounding a location on the first package surface the circuit die is couplable thereto and the circuit die is locatable therein, and, filling the enclosure with the thermal conductive material such that the gaps are filled with the thermal conductive material. An integrated circuit cooling package including the substrate, first and second enclosures and first and second thermal conductive materials is also disclosed.

The present disclosure relates to a microelectronics module featuring thermal interface material (TIM) containment for efficient and reliable top-side cooling, and a process for making the same. The microelectronics module includes a module substrate, a flip-chip die attached to the module substrate, and a heat spreader positioned above and thermally coupled to the flip-chip die. A TIM barrier, partially embedded in a mold compound, continuously surrounds the heat spreader and protrudes vertically beyond the heat spreader to define a TIM cavity over the heat spreader. A TIM section fills the TIM cavity to cover the heat spreader. A heat sink is in contact with both the TIM section and the TIM barrier, where the TIM barrier is configured to prevent the TIM section from shifting away from over the heat spreader, thereby maintaining thermal coupling between the heat sink and the heat spreader through the TIM section.

In one example, an electronic device includes a substrate having a conductive structure, an electronic component coupled to the conductive structure at a first side of the substrate, wherein the electronic component includes a first side facing the first side of the substrate and a second side opposite the first side, vertical interconnects disposed around the electronic component, wherein the vertical interconnects are coupled to the conductive structure at the first side of the substrate, a thermal body coupled to the second side of the electronic component, an interposer coupled to the vertical interconnects, wherein the interposer includes inner sidewalls defining an opening disposed around the thermal body, and an encapsulant disposed between the thermal body and the inner sidewalls of the interposer, around the vertical interconnects, and around the electronic component, wherein the thermal body is exposed from the encapsulant. Other examples and related methods are also disclosed herein.

A thermal interface layer includes pluralities of first and second particles dispersed in a polymeric binder at a total loading V in a range of about 40 volume percent to about 70 volume percent. The first and second particles have different compositions. The first particles include one or more of iron or nickel. The second particles include one or more of aluminum, magnesium, silicon, copper, or zinc. The thermal interface layer has a thermal conductivity in a thickness direction of the thermal interface layer in units of W/mK of at least K=5.10.17 V+0.002 V.sup.2.

A heat conductive sheet having excellent adhesion between an acrylic resin layer and a supporting sheet is provided. The heat conductive sheet includes a heat conductive resin layer including a heat conductive acrylic resin composition; and a supporting resin layer (supporting sheet) containing a polyvinyl acetal resin and a styrene-vinyl isoprene block copolymer. Crosslinking of the supporting sheet with acrylic monomers of the acrylic heat conductive resin layer enables improvements in adhesion between the heat conductive resin layer and the supporting sheet.

A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, a lid structure coupled to the substrate, where the lid structure includes a first compartment comprising a side surface and an inner top surface, and a thermal interface material coupled to (i) the first integrated device and (ii) the side surface and the inner top surface of the first compartment of the lid structure. The substrate includes at least one dielectric layer and a plurality of interconnects.

A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, a lid structure coupled to the substrate, where the lid structure includes a first compartment comprising a side surface and an inner top surface, and a thermal interface material coupled to (i) the first integrated device and (ii) the side surface and the inner top surface of the first compartment of the lid structure. The substrate includes at least one dielectric layer and a plurality of interconnects.

Devices and method for forming a chip package assembly, including a package substrate, a fan-out package attached to the package substrate, the fan-out package including a first semiconductor die including a first physical interface and a second semiconductor die including a second physical interface. The chip package assembly further including a heatsink structure including a heatsink base and a cavity within the heatsink base, and a thermoelectric cooler (TEC) embedded within the cavity, wherein the TEC is positioned above the first physical interface and the second physical interface.

Devices and method for forming a chip package assembly, including a package substrate, a fan-out package attached to the package substrate, the fan-out package including a first semiconductor die including a first physical interface and a second semiconductor die including a second physical interface. The chip package assembly further including a heatsink structure including a heatsink base and a cavity within the heatsink base, and a thermoelectric cooler (TEC) embedded within the cavity, wherein the TEC is positioned above the first physical interface and the second physical interface.

A circuit module includes a module substrate, a terminal interposer, and encapsulant material. The module substrate has a mounting surface and a plurality of conductive pads at the mounting surface. The terminal interposer is coupled to the mounting surface of the module substrate. The terminal interposer includes a dielectric body and a conductive terminal. The dielectric body has top, bottom, and side surfaces, and one or more mold flow channels extending from at least one of the side surfaces into the dielectric body. The conductive terminal is embedded within the dielectric body and extends between the top and bottom surfaces of the dielectric body. A proximal end of the conductive terminal is coupled to a first conductive pad of the plurality of conductive pads. The encapsulant material covers at least a portion of the mounting surface of the module substrate and extends into the one or more mold flow channels.