A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A package structure is provided. The package structure includes a first electronic component and a second electronic component, and a data access structure. The data access structure is disposed partially in a gap between the first electronic component and the second electronic component. The data access structure includes a logic portion and a storage portion. One of the logic portion and the storage portion is in the gap, and the other one of the logic portion and the storage portion is outside of the gap.

A method of forming one or more semiconductor packages includes mounting one or more semiconductor dies on the metal strip such that the one or more semiconductor dies are in a flip chip arrangement whereby terminals of the one or more semiconductor dies face the upper surface of the metal strip, forming an electrically insulating encapsulant material on the upper surface of the metal strip that encapsulates the one or more semiconductor dies, and forming package terminals that are electrically connected with the terminals of the one or more semiconductor dies, wherein the package terminals are formed from the metal strip or from metal that is deposited after removing the metal strip.

Light-emitting diode (LED) devices and more particularly die attach structures for LED chips on lead frames in LED packages are disclosed. Exemplary lead frame structures are provided with selectively plated metal layers at die attach regions for LED chips. The metal of the selectively plated metal layers is positioned to form alloys and/or intermetallic compounds with bonding materials employed for die attach of LED chips. The resulting alloys and/or intermetallic compounds form non-reflowable metal structures at and above temperatures utilized for subsequent attachment of LED packages in LED devices, thereby providing increased mechanical and electrical integrity of die attach for LED chips.

A method includes: providing a support substrate covered by a separation layer, a seed layer, a resin layer having openings; forming, through the openings, interconnection elements by depositing a solder layer, a copper pillar, and optionally a gold layer; removing the resin, and etching the non-covered portion of the seed layer; assembling the interconnection elements to an assembly comprising a substrate in which are formed first chips and second chips assembled to the first chips; wherein the interconnection elements are assembled by thermocompression onto conductive landing areas positioned on the substrate coupled to the first chips; and removing the temporary support and the separation layer.