A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

A semiconductor device includes a first semiconductor chip having a first surface and a second surface that is opposite to the first surface, a second semiconductor chip having a third surface facing the first surface and a fourth surface that is opposite to the third surface, a first dielectric layer on the first surface of the first semiconductor chip, a second dielectric layer on the third surface of the second semiconductor chip, a connection pad including a first conductive pad penetrating the first dielectric layer and a second conductive pad penetrating the second dielectric layer, and an adhesive layer between the first dielectric layer and the second dielectric layer, where the adhesive layer includes an organic dielectric material, the first conductive pad and the second conductive pad extend into the adhesive layer, and the first conductive pad directly contacts the second conductive pad.

A device comprising a memory device comprising a first memory chip comprising a first memory portion; and a first processor in memory portion, wherein the first processor in memory portion includes a first plurality of logic cells and at least one first capacitor; and a second memory chip coupled to the first memory chip.

A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

According to an embodiment, a semiconductor device includes a first chip including a substrate, and a second chip bonded to the first chip at a first surface. Each of the first chip and the second chip includes an element region, and an end region including a chip end portion. The first chip includes a plurality of first electrodes that are arranged on the first surface in the end region and are in an electrically uncoupled state. The second chip includes a plurality of second electrodes that are arranged on the first surface in the end region, are in an electrically uncoupled state, and are respectively in contact with the first electrodes.

A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate and that includes a first semiconductor substrate that includes through electrodes, and a second semiconductor chip disposed on the first semiconductor chip and that includes a second semiconductor substrate that includes an active surface and an inactive surface. The second semiconductor chip further includes a plurality of isolated heat dissipation fins that extend in a vertical direction from the inactive surface.

Provided is a semiconductor module including a main circuit portion, a plurality of circuit electrodes, a plurality of main terminals, and a plurality of wires, in each of semiconductor chips, transistor portions and diode portions have a longitudinal side in a second direction, each of semiconductor chips has a plurality of end sides including a gate-side end side, each of the gate-side end sides is arranged facing a same side in a top view, the plurality of main terminals are arranged on a same side in relation to the main circuit portion so as not to sandwich the main circuit portion in a top view, each of the plurality of wires has a bonding portion, and a longitudinal direction of the bonding portion has an angle in relation to the second direction.

Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes an inductor, and inductor includes a plurality of semiconductor builds bonded together with one on top of another, each of the plurality of semiconductor builds having two or more through-silicon vias (TSVs) that are vertically aligned with two or more TSVs of an adjacent one of the plurality of semiconductor builds; and a plurality of horizontal bars conductively connecting two of the two or more TSVs of each of the plurality of semiconductor builds, where the two or more TSVs of each of the plurality of semiconductor builds and the plurality of horizontal bars are concatenated together to have a spiral shape, in a vertical plane, that spans across the plurality of semiconductor builds. A method of manufacturing the semiconductor structure is also provided.

A semiconductor package may include: a device layer including a first semiconductor chip; a second semiconductor chip on the device layer; and a third semiconductor chip on the second semiconductor chip, wherein the device layer further includes: a molding layer surrounding the first semiconductor chip; a redistribution layer on the molding layer; and a conductive post beside the first semiconductor chip, the conductive post vertically penetrating the molding layer and connecting to the redistribution layer, wherein the redistribution layer includes: a first insulating pattern; a power delivery network (PDN) pattern in the first insulating pattern; and a redistribution pad exposed through an upper surface of the first insulating pattern, wherein the second semiconductor chip includes a first chip pad at an inactive surface of the second semiconductor chip, and wherein the PDN pattern is electrically connected to the second semiconductor chip through the redistribution pad and the first chip pad.