A device package comprising an integrated cooling assembly comprising a semiconductor device and a cold plate directly bonded to the semiconductor device. The cold plate comprises a top portion, sidewalls extending downwardly from the top portion to a backside of the semiconductor device, an inlet opening, and an outlet opening. The top portion, the sidewalls, and the backside of the semiconductor device collectively define a coolant chamber volume therebetween. The inlet opening and the outlet opening are disposed in the top portion and are in fluid communication with the coolant chamber volume. The inlet opening is disposed above a hotspot region of the semiconductor device.

According to one embodiment, a semiconductor memory device includes a first chip; and a second chip electrically connected to the first chip via a first connection pad, the second chip including a memory cell array, a first contact electrically connected to the first connection pad, and a first interconnect including a first coupling portion electrically connected to an upper end of the first contact, and a first extension continuously extending from the first coupling portion above an upper surface of the source line, wherein the first coupling portion has a shape in which a trench above the first contact is filled up to a level of a lower surface of the first extension, and the first coupling portion includes a lower surface at a level below the upper surface of the source line.

A semiconductor die is arranged at a mounting region of a surface of a substrate. A substrate includes electrically conductive leads around a die pad including a mounting region. A metallic layer is located at one or more portions of the substrate including the mounting region. A semiconductor die is arranged at a mounting region. The metallic layer is selectively exposed at portions less than all of the metallic layer to an oxidizing plasma to produce a patterned oxide layer including oxides of metallic material in the metallic layer. An electrically insulating encapsulation is molded onto the surface of the substrate to encapsulate the semiconductor die. The oxides of metallic material in the patterned oxide layer facilitate adhesion of the electrically insulating encapsulation to the surface of the substrate.

A method for sequencing a hybrid bonding process by double linking a source of dies and a target. The method may include selecting a source of dies for bonding, selecting a target on which the dies will be bonded, linking the source to the target, linking the target to the source, forming an integrated bonding product sequence that includes a first linked bonding sequence for the source and a second linked bonding sequence for the target, determining bonding process chamber allocations and process timing for the source and the target based on the integrated bonding product sequence, and bonding a die from the source to the target using the integrated bonding product sequence.

A power semiconductor module includes an AC bus bar having a first side that faces a first substrate and a second side that faces a second substrate. A first power transistor die has a drain terminal connected to a first metallic region of the first substrate and a source terminal connected to the first side of the AC bus bar. A second power transistor die has a drain terminal connected to the second side of the AC bus bar and a source terminal connected to a first metallic region of the second substrate. First and second DC bus bars are connected to the first metallic region of the respective substrates, vertically overlap one another, and protrude from a first side of a mold body that encapsulates the power transistor dies. The AC bus bar protrudes from a different side of the mold body as the DC bus bars.

A wireless transistor outline (TO) package structure includes a carrying module, a chip and a lead frame both mounted on the carrying module, a sheet-like bonding module mounted on the chip and the lead frame in a flip chip manner, and an encapsulant that covers the above components therein. A connection pad of the chip and a connection segment of the lead frame are coplanar with each other. The sheet-like bonding module includes a ceramic substrate and a plurality of circuit layers that are stacked and formed on the ceramic substrate in a direct plated copper (DPC) manner. Areas of the circuit layers gradually decrease in a direction away from the ceramic substrate, and thicknesses of the circuit layers gradually increase in the same direction. The circuit layer arranged away from the ceramic substrate connects the connection pad and the connection segment for establishing an electrical connection therebetween.

A semiconductor device and a method of forming a semiconductor device are provided. The semiconductor device includes a first die, a diamond layer and an encapsulant. The diamond layer is disposed on the first die. The encapsulant is disposed on the first die, wherein the encapsulant encapsulates the diamond layer.

A semiconductor device is provided. The semiconductor device comprises a semiconductor die comprising a semiconductor substrate and a plurality of transistors arranged at a front side of the semiconductor substrate. Further, the semiconductor die comprises a first electrically conductive structure extending from the front side of the semiconductor substrate to a backside of the semiconductor substrate and a second electrically conductive structure extending from the front side of the semiconductor substrate to the backside of the semiconductor substrate. The semiconductor device further comprises an interposer directly attached to the backside of the semiconductor substrate. The interposer comprises a first trace electrically connected to the first electrically conductive structure of the semiconductor die. Further the interposer comprises the first trace or a second trace electrically connected to the second electrically conductive structure of the semiconductor die.

An electronic device includes a substrate, a base substrate, a metal connection body, a support body, a metal body, and a via. The substrate includes one main surface with a functional element and is a piezoelectric substrate or a compound semiconductor substrate. The substrate is mounted on the base substrate such that the one main surface faces the base substrate. The metal body is in contact with the support body and includes at least a portion extending to outside the substrate in plan view from the support body. The via connects the portion of the metal body outside the substrate and the base substrate to each other and has a higher thermal conductivity than the substrate.