H10P14/6538

METHOD FOR FORMING AN ULTRAVIOLET RADIATION RESPONSIVE METAL OXIDE-CONTAINING FILM
20260018404 · 2026-01-15 ·

A method for forming ultraviolet (UV) radiation responsive metal-oxide containing film is disclosed. The method may include, depositing an UV radiation responsive metal oxide-containing film over a substrate by, heating the substrate to a deposition temperature of less than 400 C., contacting the substrate with a first vapor phase reactant comprising a metal component, a hydrogen component, and a carbon component, and contacting the substrate with a second vapor phase reactant comprising an oxygen containing precursor, wherein regions of the UV radiation responsive metal oxide-containing film have a first etch rate after UV irradiation and regions of the UV radiation responsive metal oxide-containing film not irradiated with UV radiation have a second etch rate, wherein the second etch rate is different from the first etch rate.

Silacyclic compounds and methods for depositing silicon-containing films using same

A method and composition for producing a porous low k dielectric film via chemical vapor deposition includes the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber gaseous reagents including at least one structure-forming precursor comprising an silacyclic compound, and with or without a porogen; applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a preliminary film on the substrate, wherein the preliminary film contains the porogen, and the preliminary film is deposited; and removing from the preliminary film at least a portion of the porogen contained therein and provide the film with pores and a dielectric constant of 3.0 or less. In certain embodiments, the structure-forming precursor further comprises a hardening additive.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
20260040607 · 2026-02-05 ·

The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.

RESPONSIVE LAYER FOR LOW FREQUENCY LINE WIDTH ROUGHNESS REDUCTION

Embodiments described herein relate to a method that includes forming a pattern in a resist layer that is provided over a patterning stack that includes a responsive layer. In an embodiment, the method may include transferring the pattern into the responsive layer, and applying a treatment to the responsive layer. In an embodiment, the treatment induces a tensile stress in the responsive layer and reduces a line width roughness (LWR) of the pattern.

Masking layer with post treatment

A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

Selective Directed Assembly-Based Printing of Metal Oxide Dielectric Thin Films
20260076112 · 2026-03-12 ·

A method for selectively printing metal oxide dielectric films using directed fluidic assembly is provided. The metal oxide films are printed from a liquid suspension of nanoparticulate precursors using a dip coating mechanism. The resulting films can be fully cured at about 100 C. in conjunction with UV photoannealing. The printed metal oxide films can serve as the dielectric material for a variety of passive and active electronic devices. The method reduces cost and energy consumption for the fabrication of electronic devices, and can be used to fabricate devices on flexible polymer substrates.

REFLECTOR AND/OR METHOD FOR ULTRAVIOLET CURING OF SEMICONDUCTOR
20260107731 · 2026-04-16 ·

An ultraviolet (UV) lamp assembly of a UV curing tool is provided for curing a low dielectric constant (low-k) material layer of a semiconductor wafer. The UV lamp assembly includes: a UV lamp which emits UV light; a first reflector arranged proximate to a first side of the UV lamp, the first reflector including a first surface facing the UV lamp from which UV light emitted by the UV lamp is at least partially reflected; and a UV reflective coating partially coating the first surface of the reflector. Suitably, a plurality of areas of the first surface of the reflector remain uncoated with the UV reflective coating and the plurality of uncoated areas are arranged to promote a uniform exposure of the semiconductor wafer to UV irradiation.