The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

A method and composition for producing a porous low k dielectric film via chemical vapor deposition includes the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber gaseous reagents including at least one structure-forming precursor comprising an silacyclic compound, and with or without a porogen; applying energy to the gaseous reagents in the reaction chamber to induce reaction of the gaseous reagents to deposit a preliminary film on the substrate, wherein the preliminary film contains the porogen, and the preliminary film is deposited; and removing from the preliminary film at least a portion of the porogen contained therein and provide the film with pores and a dielectric constant of 3.0 or less. In certain embodiments, the structure-forming precursor further comprises a hardening additive.

An etching method of supplying etching gases to a substrate to etch a surface of the substrate, includes a protection step of supplying amine gas to the substrate having an oxygen-containing silicon film to form a protective film for preventing etching by the etching gases on a surface of the oxygen-containing silicon film, for protecting the oxygen-containing silicon film, and a first etching step of supplying a first etching gas, which is one of the etching gases and is a fluorine-containing gas, and the amine gas to the substrate to etch the oxygen-containing silicon film.

A method for improving the elastic modulus of dense organosilica dielectric films (k2.7) without negatively impacting the film's electrical properties and with minimal to no reduction in the carbon content of the film. The method comprising the steps of: providing a substrate within a reaction chamber; introducing into the reaction chamber a gaseous composition comprising a mixture of an alkyl-alkoxysilacyclic compound and 5% or less of certain bis(alkoxy)silanes or mono-alkoxysilanes; and applying energy to the gaseous composition comprising the mixture of the alkyl-alkoxysilacyclic compound and 5% or less of certain bis(alkoxy)silanes or mono-alkoxysilanes to deposit an organosilicon film on the substrate, wherein the organosilicon film has a dielectric constant from 2.70 to 3.30, an elastic modulus of from 6 to 30 GPa, and an at. % carbon from 10 to 45 as measured by XPS.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.

A layered structure can include a porous layer over a substrate and a thermal layer coupled to pore walls of the porous layer. The porous layer can have a higher resistivity than the substrate. A stress of the porous layer can be proportional to a variance of infrared (IR) transmission data of the porous layer. The variance of IR transmission data can be no greater than 2,500. Advantageously the thermal layer can decrease stress in the porous layer, increase thermal stability of the porous layer, decrease cracking and flaking during high temperature processing, maintain high resistivity of the porous layer, and increase the quality of the epitaxial layer and/or semiconductor devices formed using the porous layer.

A method is presented for selective deposition on metals using porous low-k materials. The method includes forming alternating layers of a porous dielectric material and a first conductive material, forming a surface aligned monolayer (SAM) over the first conductive material, depositing hydroxamic acid (HA) material over the porous dielectric material, growing an oxide material over the first conductive material, removing the SAM, depositing a dielectric layer adjacent the oxide material, and replacing the oxide material with a second conductive material defining a bottom electrode.