The present invention relates to a layer formation method and, more specifically, to a semiconductor device manufacturing method for forming a semiconductor device through a low-temperature process. The layer formation method according to an embodiment of the present invention is a method for manufacturing a semiconductor device which comprises a silicon substrate containing germanium (Ge) or a substrate on which a silicon layer containing germanium (Ge) is formed, and which comprises an undoped gallium nitride (GaN) layer, an N-type gallium nitride (GaN) layer, an active layer and a P-type gallium nitride (GaN) layer, wherein a step of forming at least one gallium nitride layer from among the undoped gallium nitride (GaN) layer, the N-type gallium nitride (GaN) layer, the active layer and the P-type gallium nitride (GaN) layer comprises the steps of: a) sequentially supplying a gallium (Ga) precursor and a nitrogen (N2) precursor at 500 C. or lower, thereby forming a gallium nitride (GaN) layer on the substrate; and b) exposing the gallium nitride (GaN) layer to a hydrogen-containing plasma, and steps a) and b) are repeated multiple times.

A semiconductor structure and method for manufacturing thereof are provided. The semiconductor structure includes a silicon substrate having a first surface, a III-V layer on the first surface of the silicon substrate and over a first active region, and an isolation region in a portion of the III-V layer extended beyond the first active region. The first active region is in proximal to the first surface. The method includes the following operations. A silicon substrate having a first device region and a second device region is provided, a first active region is defined in the first device region, a III-V layer is formed on the silicon substrate, an isolation region is defined across a material interface in the III-V layer by an implantation operation, and an interconnect penetrating through the isolation region is formed.

A method of fabricating a semiconductor device includes providing a substrate, implementing a growth procedure to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, the anneal being conducted at a higher temperature than the growth procedure, and repeating the growth procedure and the anneal. The anneal is conducted at or above a decomposition temperature for the semiconductor layer.

Disclosed herein is the controlled epitaxy of Al.sub.xGa.sub.1-xAs, Al.sub.xIn.sub.1-xP, and Al.sub.xGa.sub.yIn.sub.1-x-yP by hydride vapor phase epitaxy (HVPE) through use of an external AlCl.sub.3 generator.