An MLG (multilayer graphene) device layer structure is connected with a via. The structure includes an M1 MLG interconnect device layer upon a dielectric layer. Interlayer dielectric isolates the M1 MLG interconnect device layer. An M2 MLG interconnect device layer is upon the interlayer dielectric. A metal via penetrates through the M2 MLG interconnect device layer, the interlayer dielectric and the M1 MLG interconnect device layer and makes edge contact throughout the thickness of both M1 MLG and M2 MLG layers. A method diffuses carbon from a solid phase graphene precursor through a catalyst layer to deposit MLG on a dielectric or metal layer via application of mechanical pressure at a diffusion temperature to form MLG layers.

An exemplary semiconductor structure includes a semiconductor substrate; a plurality of metal lines on top of the semiconductor substrate, each line having a line width 5 nanometers or less: a plurality of dielectric features adjacent to the metal lines; and a plurality of metal vias on top of the metal lines. Out of a random sample of 1000 vias at least 950 vias are fully-aligned to corresponding metal lines.

Integrated circuit devices are provided. An integrated circuit device includes an insulating layer and a metal via structure that is in the insulating layer. The metal via structure has a lower portion and an upper portion that is narrower than the lower portion. Moreover, the integrated circuit device includes a metal line that is on and electrically connected to the metal via structure. Related methods of forming integrated circuit devices are also provided.

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.

A semiconductor device includes a lower structure including a substrate and a cell structure on the substrate and a plurality of interconnection layers, which are stacked on the lower structure in a first direction extending perpendicular to a top surface of the substrate. An uppermost interconnection layer of the plurality of interconnection layers includes uppermost conductive lines. Each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern, an upper metal compound pattern, and a capping pattern, which are sequentially stacked in the first direction. The lower metal compound pattern, the metal pattern, and the upper metal compound pattern include a same metallic element.

A semiconductor device includes: a semiconductor substrate having first and second main surfaces; interlayer insulating films laminated on the first main surface in a thickness direction from the second main surface toward the first main surface; a top wiring arranged on a top interlayer insulating film of the plurality of interlayer insulating films, which is provided farthest from the first main surface in the thickness direction; and a passivation film arranged on the top interlayer insulating film so as to cover the top wiring. The top wiring includes a first wiring portion and a second wiring portion that extend in a first direction in plan view and are adjacent to each other in a second direction orthogonal to the first direction. A first distance between an upper surface of the top wiring and the top interlayer insulating film in the thickness direction is 2.7 m or more.

The present disclosure is directed to embodiments of a conductive structure on a conductive barrier layer that separates the conductive structure from a conductive layer on which the conductive barrier layer is present. A gap or crevice extends along respective surfaces of the conductive structure and along respective surfaces of one or more insulating layers. The gap or crevice separates the respective surfaces of the one or more insulating layers from the respective surfaces of the conductive structure. The gap or crevice provides clearance in which the conductive structure may expand into when exposed to changes in temperature. For example, when coupling a wire bond to the conductive structure, the conductive structure may increase in temperature and expand into the gap or crevice. However, even in the expanded state, respective surfaces of the conductive structure do not physically contact the respective surfaces of the one or more insulating layers.

Embodiments of the present disclosure provide a semiconductor structure including a first metal contact, where at least a portion of the first metal contact extends vertically from a substrate to a top portion of the semiconductor structure. The first metal contact having an exposed surface at the top portion of the semiconductor structure. A dielectric cap may be configured around the first metal contact. The dielectric cap is configured to electrically separate a first area of the semiconductor structure from a second area of the semiconductor structure. The first area of the semiconductor structure includes the first metal contact.

A metallic stack and a preparing method therefor, and an electronic device including the metallic stack. The metallic stack includes at least one interconnection wire layer and at least one via layer alternately arranged on a substrate. At least one pair of interconnection wire layer and via layer in the metallic stack includes interconnection wires in the interconnection wire layer and conductive vias in the via layer, wherein the interconnection wire layer is closer to the substrate than the via layer. At least a part of the interconnection wires is integrated with the conductive vias on the at least a part of the interconnection wires.