CMOS-COMPATIBLE GRAPHENE STRUCTURES, INTERCONNECTS AND FABRICATION METHODS

Abstract

An MLG (multilayer graphene) device layer structure is connected with a via. The structure includes an M1 MLG interconnect device layer upon a dielectric layer. Interlayer dielectric isolates the M1 MLG interconnect device layer. An M2 MLG interconnect device layer is upon the interlayer dielectric. A metal via penetrates through the M2 MLG interconnect device layer, the interlayer dielectric and the M1 MLG interconnect device layer and makes edge contact throughout the thickness of both M1 MLG and M2 MLG layers. A method diffuses carbon from a solid phase graphene precursor through a catalyst layer to deposit MLG on a dielectric or metal layer via application of mechanical pressure at a diffusion temperature to form MLG layers.

Claims

1. A method for forming MLG (multilayer graphene) device layers connected with a via at CMOS (complementary metal oxide semiconductor) compatible process temperatures directly onto dielectric or a metal layer, comprising: providing a dielectric or metal layer; depositing a metal or metal alloy catalyst layer on the dielctric or metal layer; depositing a solid phase graphene precursor on the catalyst layer; diffusing carbon from the graphene precursor through the catalyst layer to deposit MLG on the dielectric or metal layer via application of diffusion pressure at a diffusion temperature to form an M1 MLG layer; removing the catalyst layer; depositing interlayer dielectric on the M1 MLG layer; forming an M2 MLG layer on the interlayer dielectric via the depositing a catalyst layer, depositing a solid phase graphene precursor and diffusing carbon; opening a via hole through the entirety of the M2 MLG, interlayer dielectric and M1 MLG layer to form a via hole; and depositing via metal in the via hole to make edge contact throughout the thickness of both M1 MLG and M2 MLG layers.

2. The method of claim 1, wherein the diffusing is conducted with a diffusion pressure of 65-80 psi of pressure and a diffusion temperature is at least about 200 C.

3. The method of claim 1, wherein the graphene precursor is graphite powder.

4. The method of claim 1, wherein the graphene precursor is amorphous carbon.

5. The method of claim 1, wherein the graphene precursor is graphite slurry.

6. The method of claim 1, comprising annealing the catalyst at a temperature of less than 500 C. prior to depositing the solid phase graphene precursor.

7. The method of claim 1, wherein the via metal is one of Co, Ru, and W.

8. The method of claim 7, wherein the via metal is Co.

9. The method of claim 1, wherein the catalyst layer is Ni.

10. The method of claim 1, wherein the dielectric or metal layer and the interlayer dielectric comprise SiO.sub.2.

11. A method for forming MLG (multilayer graphene) on a metal surface, the method comprising: forming an amorphous carbon barrier layer on the metal surface; depositing a metal or metal alloy catalyst layer on the amorphous carbon barrier layer; depositing a solid phase graphene precursor on the catalyst layer; and diffusing carbon from the graphene precursor through the catalyst layer to deposit MLG on the metal surface via application of diffusion pressure at a diffusion temperature.

12. The method of claim 11, wherein the metal surface is Cu.

13. The method of claim 11, wherein the catalyst layer is Ni.

14. An MLG (multilayer graphene) device layer structure connected with a via, comprising: an M1 MLG interconnect device layer upon a dielectric layer; interlayer dielectric isolating the M1 MLG interconnect device layer; an M2 MLG interconnect device layer upon the interlayer dielectric; and a metal via through the M2 MLG interconnect device layer, the interlayer dielectric and the M1 MLG interconnect device layer, the metal via making edge contact throughout the thickness of both M1 MLG and M2 MLG layers.

15. The device layer structure of claim 14, wherein the M1 MLG layer and the M2 MLG layer are patterned.

16. The device layer structure of claim 14, wherein the dielectric layer and the interlayer dielectric comprise SiO.sub.2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1 (Prior Art) illustrates a dual damascene (DD) process for conventional metal wires as vias;

[0023] FIGS. 2A-2C show a preferred method for forming MLG-metal wire via-MLG structures in a CMOS circuit fabrication using a subtractive etching process scheme;

[0024] FIGS. 3A and 3B (Prior Art) illustrate the via layout and current density profile for a M1-via-M2 cross-section fabricated by the conventional dual damascene (DD) process; and

[0025] FIGS. 3C and 3D (Prior Art) illustrate the via layout and current density profile for a MLG-via-MLG cross-section fabricated by the preferred subtractive etching (SE) process.

[0026] FIGS. 4A-B illustrate a present method for growth of MLG directly on metallic substrates (such as Cu).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The invention provides multi-layer graphene (MLG) and doped-multilayer-graphene (DMG) structures, interconnects and fabrication methods to form the MLG and DMG structures interconnects. In a preferred embodiment method, MLG is directly grown on a dielectric (SiO.sub.2) substrate at CMOS compatible temperatures (e.g., 350 C.) in a multi-tier configuration by a pressure-assisted solid-phase precursor synthesis method and connected using metal vias, in to achieve edge contact between the MLG and the wire via in a process that meets the thermal-budget requirements of all IC processed.

[0028] In a preferred fabrication method, due to the absence of carbon diffusion through any metals or dielectrics, neither the wire (MLG or doped-MLG) nor the metal via require any diffusion-barrier layer, unlike Cu wires that must be completely encapsulated by highly resistive refractory metals that increase process complexity, cost, and the effective resistivity of Cu wires.

[0029] A preferred growth technique currently shows a uniform large coverage of 10 mm2, which can be easily scaled up to 8 inch or 12-inch wafers/substrates. This shows the tremendous potential that this process scheme possesses for direct integration into the current CMOS process.

[0030] A preferred method can also be used (also demonstrated after some modifications) to grow MLG directly on metallic substrates such as Cu, which can be employed to explore the potential benefits of using MLG as a barrier/capping layer to Cu (and other metals), eliminating the need for high-refractory metals, which increase the effective resistivity of the Cu interconnects along with cost and process complexity.

[0031] A preferred multi-level MLG interconnect with metal via structure exhibits <2% conductivity degradation over 1000 hours at room temperature without any encapsulation or barrier layer, and negligible electromigration (EM) (a typical reliability issue in interconnects) under 200 MA/cm.sup.2 of current density stress (50-folds higher than what nanoscale Cu can safely sustain) at >100 C. This makes the present via scheme the most reliable process for contacting transistors among all the currently available materials and process schemes.

[0032] The significantly higher current-carrying capacity of the preferred multi-level MLG interconnect structure can allow for a significant reduction in the MLG thickness as compared to the conventional dual-damascene process scheme leading to lower intra-wire capacitances, which can significantly improve the speed, reduce noise-coupling, and lower switching energy or power consumption in ICs. This potential of MLG interconnects to lower power is particularly significant since up to .sup.rd of the power consumption in modern microprocessors can be attributed to the interconnect capacitances. Preferred interconnect structures of the invention can enable faster, smaller, lighter, more flexible, more reliable, more energy-efficient, and more cost-effective ICs.

[0033] In a preferred method, MLG is directly grown on a dielectric (SiO.sub.2) substrate at 350 C. in a multi-tier configuration by a pressure-assisted solid-phase diffusion and connected using metal vias, while meeting thermal-budget requirements of all IC processes.

[0034] Preferred methods join MLGs with an edge-contact configuration, which is the most preferred manner of connecting to the MLGs to minimize the interface contact resistance, and hence, the overall via resistance. This translates to faster speed for signal propagation and clock distribution in chips as well as much lower resistive losses (IR-drop) during on-chip power distribution.

[0035] Preferred methods avoid carbon diffusion through any metals or dielectrics, neither the wire (MLG or doped-MLG) nor the metal via require any diffusion-barrier layer, unlike Cu wires that must be completely encapsulated by highly resistive refractory metals that increase process complexity, cost, and the effective resistivity of Cu wires.

[0036] Preferred methods demonstrated in experiments a uniform large coverage of 10 mm.sup.2, which can be easily scaled up to 8 inch or 12-inch wafers/substrates. This demonstrates that methods can be directly integrated into the current state-of-the-art CMOS process.

[0037] A preferred method (as demonstrated experimentally) can grow MLG directly on metallic substrates such as Cu. One application of this method is to employ MLG as a capping layer to Cu, eliminating the need for high-refractory metals, which increase the effective resistivity of the Cu interconnects along with cost and process complexity.

[0038] A preferred device structure of a multi-level MLG interconnect with metal via scheme exhibits <2% conductivity degradation over 1000 hours at room temperature without any encapsulation or barrier layer, and negligible electromigration (EM) (a typical reliability issue in interconnects) under 200 MA/cm.sup.2 of current density stress (50-folds higher than what nanoscale Cu can safely sustain) at >100 C. Such a via structure greatly exceeds the most reliable current processes for contacting transistors among all the currently available materials and process schemes.

[0039] Preferred multi-level MLG interconnect via structures provide significantly higher current-carrying capacity compared to conventional structures, which can allow for a significant reduction in the MLG thickness as compared to the conventional dual-damascene process scheme leading to lower intra-wire capacitances, which can significantly improve the speed, reduce noise-coupling, and lower the power consumption in ICs. The present multi-level MLG interconnect via structures can lower power consumption, which is particularly significant since up to .sup.rd of the power consumption in modern microprocessors can be attributed to the interconnect capacitances.

[0040] Preferred embodiments use different solid phase graphene precursors. One solid phase precursor is graphite powder. Another solid phase precursor is a graphite slurry. An additional solid phase graphite precursor is an amorphous carbon (a-carbon) layer. The method employing deposited a-carbon layer can provide significant advantages over the graphite powder and graphite slurry for high-volume CMOS manufacturing.

[0041] Experiments deposited MLG on SiO.sub.2, which is a preferred and widely used dielectric. However, the present methods for forming MLG can form the MLG on any dielectric that can withstand the thermal requirements of the process (350-400 C.).

[0042] Preferred embodiments of the invention will now be discussed with respect to experiments and drawings. Broader aspects of the invention will be understood by artisans in view of the general knowledge in the art and the description of the experiments that follows.

[0043] FIGS. 2A-2B illustrate a preferred method for graphene growth directly on dielectric at CMOS processing temperatures, and FIG. 2C illustrates a preferred method for formation of an MLG-via-MLG structure with edge contact between a metal via and two connected MLG layers. The process in FIGS. 2A-2B can reliably grow large-area, uniform, and good-quality MLG at multiple levels, and the process in FIG. 2C connects the multiple levels with an edge-contact metal via. The uniform MLG can be patterned into interconnect patterns via conventional masked etching techniques. For example, an experiment patterned MLG layers by oxygen ICP etching with a metal mask, which is subsequently removed by wet etching.

[0044] In FIG. 2A, a first step 20 cleans a silicon dioxide layer on a silicon substate. The SiO.sub.2, e.g., 200 nm will serve as the inter-layer dielectric in a MLG-via-MLG structure to be formed. In step 22, a metal or alloy catalyst is deposited, for example nickel. Other metals and alloys such as Co, Fe, Cu, Co-Ni alloy can also be utilized for growing graphene. However, the thickness, quality, area coverage of the resultant graphene is a critical function of the choice of the metal catalyst. Ni is the best possible and most preferred choice. In an experiment, 100 nm thick Ni was deposited via E-beam evaporation at a chamber pressure of around 310.sup.6 Torr. Thickness in the range of 50 nm to 200 nm can also be used. Generally, higher metal catalyst thicknesses decrease the thickness of the resultant MLG layer, and lower metal catalyst thicknesses increase the thickness of the resultant MLG layer (for the same growth time), as the carbon atoms need to diffuse through the grains and grains boundaries of the metal catalyst and nucleate at the Ni/SiO2 interface. Low temperature annealing below 450 C., e.g. 350 C. for 2 hours in a H2/Ar environment, improves the quality of the deposited metal catalyst (Ni). Annealing can be performed in vacuum, Ar, H.sub.2, N.sub.2, O.sub.2, or forming gas, but a combination of H.sub.2/Ar is preferred because the presence of H.sub.2 with an inert Ar background helps in significantly improving the metal quality (by increasing the metal grain size). Annealing just before the actual growth step significantly improved the coverage and the growth quality. Anneal is preferably conducted at the same temperature used for other steps to not only reduce the overall process complexity, but also to satisfy CMOS BEOL thermal budget requirements. A next step 24 deposits a solid-phase graphene precursor, and three options as shown in FIG. 2A, specifically an amorphous carbon option, a graphene slurry option and a graphene powder option. Powder can be sprinkled uniformly across the wafer, roughly around 100 m thick. The amorphous carbon (10-15 nm in thickness) was deposited in experiments via E-beam evaporation, which was the same technique used for depositing the Ni metal catalyst. In general, a relationship between the thickness of the amorphous carbon precursor to the thickness of the resultant MLG thin film is a function of the super saturation concentration of carbon in the selected catalyst. A 1:1 ratio between the amorphous carbon thin film thickness and the resultant MLG thickness provides a reasonable guide. A slurry is a solution of an organic solvent with graphite powder, which can be uniformly spread across the wafer and heated, so that the organic solvent can be evaporated. The resultant thin film is about 10-20 nm thick.

[0045] The process continues in FIG. 2B step 26, with the formed graphene precursor being subject to pressure and temperature sufficient to causing carbon to diffuse through the Ni catalyst and form a graphene layer on the SiO.sub.2. As an example, 65-80 psi of pressure is applied at a temperature of at least about 350 C. for around 60 mins to result in 20 nm of multi-layer graphene (MLG). A minimum temperature for the diffusion can be as low as 200 C. Maximum temps to accomplish diffusion could be as high as 1000 C., However, CMOS-compatibility requires maximum temperatures below 500 C. Afterwards, oxygen cleaning in step 28 removes any excess graphene precursor and then the metal catalyst is etched away in step 30 to leave a high-quality graphene layer on the SiO.sub.2. Subtractive etching is performed in step 32 to pattern an MLG interconnect.

[0046] The process in FIG. 2C can be used to produced bottom 40 and top 42 MLG (which can be referred to as M1 and M2) layers, which can also be patterned by conventional masked etching techniques. The M1 and M2 layers 40 and 42 are formed according to the FIGS. 2A-2B process directly on dielectric layers, e.g., SiO.sub.2 layers 44 and 46. Plasma enhanced chemical vapor deposition (PECVD) was used in experiments for depositing SiO.sub.2, but dielectric can be formed by any other technique. Dielectric with uniform coverage and thickness is typical, but methods of the invention are versatile enough to form MLG on arbitrary surface topologies. An additional dielectric layer 48 can form part of an interconnect pattern of the M2 MLG layer 42. In a step 50, the dielectric layer 46 is formed as an inter-dielectric layer and is prepared as in FIGS. 2A-2B for the formation of the top MLG M2 layer 42, after which additional dielectric 48 is formed. In step 52, a hole 54 is opened through the layers down to dielectric layer 44. In step 56, metal is deposited in the hole 54 to form via 58, which advantageously makes edge contact through the entire thickness of each of the bottom 40 and top 42 MLG M1 and M2 layers.

[0047] Various metals can be used for the via 58. Density functional theory (DFT) simulations conducted among Co, Ru, and W reveal that they possess almost identical edge-contact resistance to the MLG. However, the higher activation energy and lower resistivity of Co as compared to Ru and W. implies its higher tolerance to EM (Electromigration) and SH (Self-Heating), making it the better choice and preferred metal for the via 58 for a multi-level MLG wire-via structure.

[0048] This edge contact avoids current crowding of top and bottom contact (FIGS. 3A and 3B), as shown in FIGS. 3C and 3D. The edge contact structure exhibits significant alleviation of current crowding and SH effects compared to the conventional DD process, mainly due to the current re-distribution caused by the edge-contact resistance between via and the MLG wire as shown in FIGS. 3B and 3D. MLG offers higher electrical conductivity and EM resistance compared with SE-Co and Ru, especially at smaller aspect ratios. Therefore, despite the addition of the edge-contact resistance between MLG and metal via increases the overall via resistance, testing shows that the FO4 delay remains invariant w.r. t the total via resistance.

[0049] The quality of MLG layers and via performance was tested experimentally. Sharp G and 2D peaks in the single point Raman spectrum data. TEM images verified uniform high-quality growth. Top MLG M2 42 fabricated over the inter-layer dielectric (ILD) 46 under exhibited comparable quality and thickness as the bottom MLG 40, as evidenced from the single point Raman spectra and the uniform large area Raman map observed experimentally. XPS was used to determine C1s content in the bottom MLG film, and showed exact peak position (1202.3 eV) and atomic composition (83%) corresponding to the C=C sp2 bond that can also be observed in the conventional CVD grown MLG, which confirms the high-quality growth of the solid-phase MLG, without requiring the high and CMOS incompatible temperatures of >800 C. for CVD grown MLG.

[0050] An experimental fabrication consistent with FIGS. 2A-2C, demonstrated a two-level SE (Subtractive-Etching)-MLG interconnect structure using Co via where the via hole is etched through the wires and ILD using a single damascene process. The experimental structure included 20 nm thick MLG for both levels. Although unintentional, the use of FeCl.sub.3 solution for removing Ni catalyst in step 30 provides surface-doping with presence of Fe at both the top and bottom MLG surfaces, which can lower the MLG resistivity. The via resistance was measured and the minimum contact resistance is estimated to be 137 -m for 20-nm thick Co-MLG edge-contacts. This value also corroborates the partial surface doping claim of MLG caused by FeCl.sub.3, as it lies between the theoretically estimated (by DFT) edge-contact resistance values of doped-and undoped-MLG with Co. Constant current stress tests showed that via increased resistance was <2% over >40 hrs, indicating negligible EM in the Co via and/or at the Co-MLG contacts.

[0051] FIGS. 4A-4B show a preferred method for formation of MLG directly on a Cu layer. In step 60, a stack is formed that includes SiO.sub.2 on a silicon substrate, followed by a Cu layer, a thin amorphous carbon barrier layer, a Nickel catalyst layer, and a solid phase graphene precursor, which can be graphite power, as shown, amorphous carbon or a graphite slurry as shown in FIG. 2A. The thin amorphous carbon layer prevents Cu and Ni layers from inter-diffusion and aids the graphene growth process by acting as an additional source of readily available carbon at the Cu interface and gets completely consumed during the MLG growth. Applicant of pressure in step 64 as in the manner of step 26 in FIG. 2B carbon to diffuse through the Ni catalyst and form a graphene layer on the Cu. After the graphene layer forms, cleaning and nickel etching are conducted as in steps 28 and 30 of FIG. 2B. Cleaning is conducted to remove any graphite formation on the Ni substrate using a O.sub.2 plasma. Ni etching removed the Ni catalyst metal layer via wet etching using a FeCl.sub.3 solution, but other material removal process can be used including dry etching. Subsequently, the MLG layer is etched via a subtractive process, such as a process using oxygen plasma.

[0052] Experiments were also conducted to verify the method of FIGS. 4A-4B. In the experiments, a 300 nm SiO.sub.2 layer was formed on Si wafer, on which 100 nm Cu, 2 nm amorphous carbon, and 100 nm Ni layers are deposited via E-beam deposition. The graphite precursor is then uniformly applied across the resultant stack, e.g. 100 m of graphite powder. Raman spectra revealed the formation of the high-quality MLG grown directly on Cu at 350 C., which was also verified by a layered structure visible in TEM images. Patterned interconnect MLG layers edge contacted with metal vias as discussed above were also formed in additional experiments. In an example experiment, bottom-MLG is grown as in FIGS. 2A-2B and then patterned by oxygen ICP etching with metal mask, which is subsequently removed by wet etching. 200 nm thick SiO.sub.2 ILD is deposited after contacts and pads (15 nm Ni/150 nm Au) are defined to connect the bottom-MLG. The top-MLG is patterned to form an overlapping region with the bottom-MLG, followed by patterning of contacts and pads for the top-MLG. A via hole (widths ranging from 200 nm to 2 m) is opened by three-steps of oxygen-, CHF.sub.3, and oxygen-ICP to etch the top-MLG, ILD, and bottom-MLG, respectively, with a photoresist mask. A 220 nm thick Co is deposited by thermal evaporation (<100 C.) to fill the via hole at slow deposition rate to ensure full metal fill. Finally, ILD on top of bottom pads are etched to allow electrical contacts. The wire/via width can be scaled further with more advanced lithography techniques known in the art.

[0053] While specific embodiments of the present invention have been shown and described, it should be understood that other modifications, substitutions and alternatives are apparent to one of ordinary skill in the art. Such modifications, substitutions and alternatives can be made without departing from the spirit and scope of the invention, which should be determined from the appended claims.

[0054] Various features of the invention are set forth in the appended claims.