A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

A semiconductor package including: a semiconductor package comprising a first semiconductor chip which includes a first face and a second face opposite to each other in a first direction, a first insulating layer which is disposed on the first face, and includes vias connected to each connecting pad of the first semiconductor chip, redistribution patterns which are disposed on the first insulating layer, under bump metal layers (UBM) which are respectively disposed on the redistribution patterns, a second insulating layer which covers a part of each of the redistribution patterns, and solder bumps which are respectively disposed on the UBMs, wherein the first insulating layer includes a third face and a fourth face opposite to the third face in the first direction, wherein the third face is adjacent to the first face, and a part of the fourth face does not overlap the second insulating layer in the first direction.

A bonding pad structure and a method of manufacturing a bonding pad structure are provided. The bonding pad structure includes a carrier, a first conductive layer disposed over the carrier, a second conductive layer disposed on the first conductive layer and contacting the first conductive layer, and a third conductive layer disposed on the second conductive layer and contacting the second conductive layer. The bonding pad structure also includes a first passivation layer disposed on the first conductive layer and contacting at least one of the first conductive layer or the second conductive layer. An upper surface of the third conductive layer facing away from the carrier is exposed from the first passivation layer.

Provided are a package structure and a method of forming the same. The package structure includes a bottom package having a first sidewall and a second sidewall opposite to each other; a hybrid path layer disposed on the bottom package, wherein the hybrid path layer comprises an optical path layer and an electrical path layer, and at least one optical path of the optical path layer extends from the first sidewall of the bottom package beyond a center of the bottom package; and a plurality of dies bonded onto the hybrid path layer.

A method is described. The method includes creating a partial through-substrate via (TSV) plug in a front side of a wafer, the partial TSV having a front side and a back side. The back side of the partial TSV extending toward a front side of a substrate but not into a bulk of the substrate. A cavity is etched in a back side of the wafer that exposes the partial TSV plug. An insulator is applied to the etched back side of the wafer. A portion of the partial TSV plug is exposed by removing a portion of the insulator. A conductive material is deposited to connect the exposed, partial TSV plug to a surface on the back side of the wafer.

A semiconductor structure includes a semiconductor chip, a substrate and a plurality of bump segments. The bump segments include a first group of bump segments and a second group of bump segments collectively extended from an active surface of the semiconductor chip toward the substrate. Each bump segment of the second group of bump segments has a cross-sectional area greater than a cross-sectional area of each bump segment of the first group of bump segments. The first group of bump segments includes a first bump segment and a second bump segment. Each of the first bump segment and the second bump segment includes a tapered side surface exposed to an environment outside the bump segments. A portion of a bottom surface of the second bump segment is stacked on the first bump segment, and another portion of the bottom surface of the second bump segment is exposed to the environment.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

In one example, a semiconductor device can comprise a unit substrate comprising a unit conductive structure and a unit dielectric structure, and an electronic component coupled to the unit conductive structure. The unit substrate can comprise a portion of a singulated subpanel substrate of a panel substrate. Other examples and related methods are also disclosed herein.

An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.