Methods of forming an integrated device, and in particular forming one or more sample wells in an integrated device, are described. The methods may involve forming a metal stack over a cladding layer, forming an aperture in the metal stack, forming first spacer material within the aperture, and forming a sample well by removing some of the cladding layer to extend a depth of the aperture into the cladding layer. In the resulting sample well, at least one portion of the first spacer material is in contact with at least one layer of the metal stack.

A substrate processing apparatus includes: a chamber; and a processing gas supply unit connected to the chamber via a processing gas supply flow path and configured to supply a processing gas. The processing gas supply unit includes a raw material cartridge that includes a raw material tank that accommodates a porous member containing a metal-organic framework adsorbed with gas molecules of a raw material of the processing gas; a main body configured to communicate the raw material tank and the processing gas supply flow path with each other when the raw material cartridge is attached; and a desorption mechanism configured to desorb the gas molecules of the raw material of the processing gas and allow the gas molecules to flow out as the processing gas to the processing gas supply flow path while the raw material cartridge is attached to the main body.

In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Methods for filling a recessed feature on a substrate are disclosed. The methods disclosed include depositing a flowable layer structure on the substrate and heating the flowable layer structure above the glass transition temperature of the flowable layer structure. Methods for depositing the flowable layer structure include depositing an aluminum oxide based flowable layer structure employing atomic layer deposition processes.

Provided are high quality metal-nitride, such as aluminum nitride (AlN), films for heat dissipation and heat spreading applications, methods of preparing the same, and deposition of high thermal conductivity heat spreading layers for use in RF devices such as power amplifiers, high electron mobility transistors, etc. Aspects of the inventive concept can be used to enable heterogeneously integrated compound semiconductor on silicon devices or can be used in in non-RF applications as the power densities of these highly scaled microelectronic devices continues to increase.

An aluminum nitride sintered body contains 1 to 5% by weight of yttrium oxide (Y.sub.2O.sub.3), 10 to 100 ppm by weight of titanium (Ti), and the balance being aluminum nitride (AlN). Accordingly, a volume resistance value and thermal conductivity at a high temperature are improved, and the generation of impurities during a semiconductor manufacturing process can be suppressed.

Disclosed are methods and systems for depositing layers comprising a metal and nitrogen. The layers are formed onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

Disclosed are methods and systems for depositing layers comprising a metal and nitrogen. The layers are formed onto a surface of a substrate. The deposition process may be a cyclical deposition process. Exemplary structures in which the layers may be incorporated include field effect transistors, VNAND cells, metal-insulator-metal (MIM) structures, and DRAM capacitors.

A semiconductor device that can be miniaturized or highly integrated is provided.

The semiconductor device includes a first conductor, a second conductor over the first conductor, a first insulator covering the second conductor, a first oxide over the first insulator, and a second oxide over the first oxide, an opening overlapping with at least part of the first conductor is provided in the first oxide and the first insulator, and the second oxide is electrically connected to the first conductor through the opening.

Embodiments of improved process flows and methods are provided to pattern a semiconductor substrate using direct self-assembly (DSA) of metalate salt ionic liquid crystals (ILCs) having metalate anions. After self-assembly of the metalate salt ILCs into ordered structures, an oxidation process is used to remove the organic components of the ordered structures and convert the metalate anions into metal oxide patterns. In addition to providing a robust metal oxide pattern, which can be transferred to the underlying substrate, the process flows and methods disclosed herein enable ILCs to be used as pitch multipliers in advanced patterning techniques.