RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A Doherty amplifier includes a carrier amplifier and a peak amplifier. Each of the carrier amplifier and the peak amplifier is a differential amplifier including a first phase amplifier and a second phase amplifier. The Doherty amplifier also includes a balun configured to synthesize an output signal of the carrier amplifier and an output signal of the peak amplifier. The carrier amplifier and the peak amplifier are formed in an integrated circuit. The balun is formed on a printed wiring board on which the integrated circuit is mounted.

A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.

A method for making an electronic package is provided. The method includes providing a substrate strip comprising substrate assemblies, each substrate assembly comprises a first substrate and a second substrate connected to the first substrate via a flexible link, the first substrate comprises a first mounting surface, the second substrate comprises a second mounting surface that is not at a same side of the substrate assembly as the first mounting surface; disposing the substrate strip on a first carrier; attaching a first electronic component onto the first mounting surface; disposing the substrate strip on a second carrier with a plurality of cavities, the first electronic component is received within one of the plurality of cavities; attaching a second electronic component onto the second mounting surface; singulating the substrate assemblies from each other; and bending the flexible link to form an angle between the first substrate and the second substrate.

In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.

A method of fabricating an electronic device includes forming a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate having a first level, a second level, and a filter circuit in the first and second levels. The filter circuit includes a filter input terminal, a first capacitor, a first inductor, a second capacitor, a second inductor, a filter output terminal, and a reference terminal. The semiconductor die is attached to the multilevel package substrate and has a conductive structure coupled to one of the terminals of the filter circuit, and the package structure encloses the semiconductor die and a portion of the multilevel package substrate.

A dual sided molded package has a substrate with pads of varying size configured to receive electrically conductive interconnect members thereon. The pads include first pads that have a larger surface area than a surface area of second pads. In one implementation, one or more first pads are proximate the corners of the substrate. First interconnect members are attached to the first pads and second interconnect members are attached to the second pads. The first interconnect members have an exposed solderable area that is substantially equal to the surface area of the first pads, and the second interconnect members have an exposed solderable area that is substantially equal to the surface area of the second pads. The first exposed solderable area is larger than the second exposed solderable area.

An integrated electronic device includes at least one component produced on a carrier structure including a semiconductor substrate, and an interconnection track (8) that runs over the carrier structure from the component to a lateral face of the device. The interconnection track includes a layer of oxidizable material bearing a continuous layer of conductive material. The layer of oxidizable material is discontinuous. A method for producing such an integrated electronic device is also disclosed herein.