A semiconductor device with doped shallow trench isolation (STI) structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure, depositing an oxide liner surrounding the superlattice structure and the fin structure in a first deposition process, forming a dopant source liner on the oxide liner, depositing an oxide fill layer on the dopant source liner in a second deposition process different from the first deposition process, performing a doping process to form a doped oxide liner and a doped oxide fill layer, removing portions of the doped oxide liner, the doped oxide fill layer, and the dopant source liner from sidewalls of the superlattice structure, and forming a gate structure on the fin structure and surrounding the first nanostructured layers.

A SiC semiconductor device manufacturing method includes a step of etching a surface of a SiC substrate 1 with H.sub.2 gas under Si-excess atmosphere within a temperature range of 1000 C. to 1350 C., a step of depositing, by a CVD method, a SiO.sub.2 film 2 on the SiC substrate 1 at such a temperature that the SiC substrate 1 is not oxidized, and a step of thermally treating the SiC substrate 1, on which the SiO.sub.2 film 2 is deposited, in NO gas atmosphere within a temperature range of 1150 C. to 1350 C.

A semiconductor device structure and a formation method are provided. The method includes forming a sacrificial base layer over a substrate and forming a semiconductor stack over the sacrificial base layer. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack to partially cover the sacrificial base layer, the semiconductor layers, and the sacrificial layers. The method further includes removing the sacrificial base layer to form a recess between the substrate and the semiconductor stack. In addition, the method includes forming a metal-containing dielectric structure to partially or completely fill the recess. The metal-containing dielectric structure has multiple sub-layers.

A method of fabricating a semiconductor device is provided. The method includes forming a lower transistor device including a plurality of lower semiconductor layers and a lower gate stack surrounding the plurality of lower semiconductor layers. The lower gate stack includes a gradient layer on each lower semiconductor layer included in the plurality of lower semiconductor layers, and a lower interfacial layer on the gradient layer. The method further includes forming an upper transistor device on top of the lower transistor device. The upper transistor devices includes a plurality of upper semiconductor layers and an upper gate stack surrounding the plurality of upper semiconductor layers. The upper gate stack includes an upper interfacial layer on the plurality of upper semiconductor layers. A reliability anneal is performed on the upper transistor device, while the lower interfacial layer prevents regrowth of the gradient layer when performing the reliability anneal.