A device includes a source region and a drain region over a substrate. The device further includes a gate structure at least partially between the source region and the drain region, and a gate contact over the gate structure. The gate contact has an upper portion and a lower portion below the upper portion. The lower portion is more tapered than the upper portion.

Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer over a conductive interconnect line, the ILD layer having a trench therein, the trench exposing a portion of the conductive interconnect line. A dielectric liner layer is along a top surface of the ILD layer and along sidewalls of the trench, the dielectric liner layer having an opening therein, the opening over the portion of the conductive interconnect line. A conductive via structure is in the trench and between portions of the dielectric liner layer along the sidewalls of the trench, the conductive via structure having a portion extending vertically beneath the dielectric liner layer and in contact with the portion of the conductive interconnect line.

A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the mask covers an exposed surface of the second semiconductor region within the second opening, performing an amorphization ion implant process to amorphize an exposed surface of the first semiconductor region within the first opening, performing a removal process to remove the mask, performing a selective epitaxial deposition process, to epitaxially form a contact layer on the exposed surface of the second semiconductor region, and performing a recrystallization anneal process to recrystallize the amorphized surface of the first semiconductor region.

A semiconductor device includes a first structure including a first insulating layer and a first conductive wiring arranged on the first insulating layer, a second-1 insulating layer arranged above the first structure in a first direction, a via hole penetrating the second-1 insulating layer in the first direction, a barrier layer arranged at a lower side of the via hole, and a via plug electrically connected to the first conductive wiring and arranged to fill a remaining space in an internal space of the via hole, excluding the barrier layer.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

A method of forming a semiconductor device includes the following operations. A substrate is provided with an electric component. A composite dielectric layer is formed on the substrate and covers the electric component. An opening is formed through the composite dielectric layer. A directional etching process is performed to widen an upper portion of the opening. A metal feature is formed in the opening.

Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0 C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0 C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

A manufacturing method of a semiconductor structure including following steps is provided. A patterned photoresist layer is formed on a substrate by a lithography process. The patterned photoresist layer includes a first opening and a second opening. The first opening includes a first inclined sidewall. An etching process is performed on the substrate by using the patterned photoresist layer as a mask to form a third opening corresponding to the first opening and a fourth opening corresponding to the second opening in the substrate. The third opening includes a second inclined sidewall. A conductive layer is formed on the substrate. The conductive layer fills the third opening and the fourth opening. A portion of the conductive layer is removed by using the conductive layer located in the third opening as a stop layer to form a mark in the third opening and a TSV in the fourth opening.

Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.

In an embodiment, a method may include forming a via hole in a dielectric layer, performing a directional etching process to enlarge one side of the via hole, and after the directional etching process, forming a trench hole in the dielectric layer, where the trench hole is above and spatially connected with the via hole, where the directional etching creates an asymmetrical profile having a first side width and a second side width measured from a center of the via hole, the second side width being greater than the first side width. The method may further include filling the via hole and the trench hole with a conductive material.