In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

A semiconductor device includes a first III-V nitride-based layer, a second III-V nitride-based layer, a nitride-based transition layer, and a nitride-based transistor. The first III-V nitride-based layer is disposed over a substrate by applying a first V/III ratio in a first range. The second III-V nitride-based layer is disposed over the first III-V nitride-based layer by applying a second V/III ratio in a second range, in which the first range and the second range are mutually exclusive. The nitride-based transition layer is disposed between the first III-V nitride-based layer and the second III-V nitride-based layer to connect the first III-V nitride-based layer with the second III-V nitride-based layer, in which the nitride-based transition layer is formed by applying a third V/III ratio in a third range between the first range and second range. The nitride-based transistor is disposed over the second III-V nitride-based layer.

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

Solar cell structures comprising a plurality of solar cells, wherein each solar cell is separated from adjacent solar cell via a tunnel junction and/or a resonant tunneling structure (RTS), are described. Solar cells are implemented on Ge, Si, GaN, sapphire, and glass substrates. Each of the plurality of solar cells is at least partially constructed from a cell material which harnesses photons having energies in a predetermined energy range. In one embodiment each solar cell comprises of at least two sub-cells. It also describes a nano-patterned region/layer to implement high efficiency tandem/multi-junction solar cells that reduces dislocation density due to mismatch in lattice constants in the case of single crystalline and/or polycrystalline solar cells. Finally, solar structure could be used as light-emitting diodes when biased in forward biasing mode. The mode of operation could be determined by a programmed microprocessor.

A semiconductor device includes channel structures spaced apart in a vertical direction; lower/upper first gate insulation patterns contacting lower/upper surfaces of the channel structures; a gate electrode surrounding lower/upper surfaces and a sidewall of the channel structures; and source/drain layers at sides of the gate electrode, wherein the channel structures include first/second 2D material layers stacked in the vertical direction, the first 2D material layer includes a semiconducting TMD including a first transition metal and first chalcogen elements that are bonded at lower/upper sides of the first transition metal, the second 2D material layer includes a second transition metal and a second chalcogen element, the second chalcogen element being bonded at a lower side of the second transition metal, and the second transition metal included in the second 2D material layer is covalently or ionically bonded with an element of the upper first gate insulation pattern.

Methods for transferring graphene to substrates include at least a method for transferring a graphene-metal bilayer to a substrate to form a laminate thereof. The method can include applying a first continuous polymer layer to a graphene layer of the graphene-metal bilayer; applying a first discontinuous polymer layer to the first continuous polymer layer; applying a second continuous polymer layer to a metal layer of the graphene-metal bilayer; applying a second discontinuous polymer layer to the second continuous polymer layer; etching the first continuous polymer layer with a first etchant through the first discontinuous polymer layer; laminating the substrate by pressing the face of the graphene layer into a surface of the substrate; etching the second continuous polymer layer with a second etchant through the second discontinuous polymer layer, thereby transferring the graphene-metal bilayer to the substrate to form the laminate.

Porous III-nitrides having controlled/tuned optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such porous III-nitrides.

A semiconductor laminate at least including: a base; a buffer layer; and a crystalline metal oxide semiconductor film containing at least one metal element and having a corundum structure, the semiconductor laminate having the buffer layer on a main surface of the base directly or via another layer, the semiconductor laminate having the crystalline metal oxide semiconductor film on the buffer layer. The buffer layer is a laminate structure of a plurality of buffer films each with a different composition, and at least two buffer films of the plurality of buffer films have a film thickness of 200 nm or more and 650 nm or less.

A method for manufacturing a group III nitride semiconductor substrate, that includes: growing a first AlN buffer layer on an Si substrate at a first growth temperature; growing a second AlN buffer layer on the first AlN buffer layer at a second growth temperature higher than the first growth temperature; and growing a group III nitride semiconductor layer on the second AlN buffer layer, wherein an Al raw material and an N raw material are alternately repeatedly fed in the growing the first AlN buffer layer.