A header for a semiconductor package, includes an eyelet having a through hole penetrating the eyelet from an upper surface to a lower surface of the eyelet, a first lead inserted inside the through hole, and an insulating substrate disposed on the upper surface of the eyelet, and provided with a first through hole at a position overlapping one end of the first lead in a plan view. The insulating substrate has a thermal conductivity lower than a thermal conductivity of the first lead. A first conductive layer is formed on an inner wall defining the first through hole, and the first conductive layer extends to an upper surface of the insulating substrate. The one end of the first lead is electrically connected to the first conductive layer, and a space is provided above the one end of the first lead inside the first through hole.

An electronic component is provided. The component includes: a base member, a Peltier element; a semiconductor element placed on a placement surface of the base member via the Peltier element; and a frame member arranged so as to surround a side surface of the semiconductor element. A first electrode provided in the semiconductor element is connected, via a conductive wire, to a second electrode provided in the frame member, and the base member and the frame member are bonded by a bonding member having a lower thermal conductivity than the base member.

Semiconductor devices having integrated cooling systems, and associated systems and methods, are disclosed herein. An example of a semiconductor device according to the present technology is a system-in-package device that includes a base substrate, a processing device and a high-bandwidth memory device that are each integrated with the base substrate, and a package cooling device that is thermally coupled to the processing device and the high-bandwidth memory device. In some embodiments, the package cooling device includes a first heat spreader thermally coupled to an upper surface of the processing device, a second heat spreader thermally coupled to an upper surface of the high-bandwidth memory device, a thermoelectric cooling device positioned between and thermally coupled to a portion of the first heat spreader and the second heat spreader, and a heat exchanger thermally coupled to the first heat spreader.

Semiconductor devices having integrated cooling systems, and associated systems and methods, are disclosed herein. An example of a semiconductor device according to the present technology is a system-in-package device that includes a base substrate, a processing device and a high-bandwidth memory device that are each integrated with the base substrate, and a package cooling device that is thermally coupled to the processing device and the high-bandwidth memory device. In some embodiments, the package cooling device includes a first heat spreader thermally coupled to an upper surface of the processing device, a second heat spreader thermally coupled to an upper surface of the high-bandwidth memory device, a thermoelectric cooling device positioned between and thermally coupled to a portion of the first heat spreader and the second heat spreader, and a heat exchanger thermally coupled to the first heat spreader.

A semiconductor package includes a substrate with electrical conductors, one or more semiconductor dies disposed on the substrate and electrically connected with the electrical conductors of the substrate, and a lid disposed on the substrate. The one or more semiconductor dies are disposed in a space enclosed by the substrate and the lid. At least one thermoelectric device is at least partly embedded in the lid. The at least one thermoelectric device may be operated to cool the semiconductor package, or to heat the semiconductor package. A controller for the at least one thermoelectric device may be implemented in the one or more semiconductor dies.

A thermal dissipation system for an integrated circuit (IC) includes an IC disposed on a substrate and a heat sink including a body having a first surface including a first part coupled to a side of the IC opposite the substrate and a second part disposed away from the IC and positioned in spaced relation to the substrate. A set of legs support at least the second part of the body in spaced relation to the substrate. The set of legs may be part of the body or may be part of a carrier disposed between the second part of the first surface of the body and the substrate. The carrier includes an opening through which a portion of the substrate that includes the first part that is coupled to the side of the IC opposite the substrate extends.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

A method includes forming a package component, including forming a thermal via extending through a substrate; and bonding a die to the thermal via; attaching the thermal via of the package component to a first conductive pad of a package substrate, wherein the package substrate includes a heat pipe underneath the first conductive pad; and attaching a support structure to a second conductive pad of the package substrate, wherein the heat pipe is underneath the second conductive pad, wherein the support structure includes a first thermoelectric cooler.

An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device. An integrated circuit containing an embedded resistor in close proximity to an embedded thermoelectric device composed of thermoelectric elements and at least one switch to disconnect at least one thermoelectric element from the thermoelectric device. Methods for testing embedded thermoelectric devices.

In some aspects, the disclosed technology provides microelectronic devices which can effectively dissipate heat and methods of forming the disclosed microelectronic devices. In some embodiments, a disclosed device may include a first integrated device die. The disclosed device may further include a thermoelectric element bonded to the first integrated device die. The disclosed device may further include a heat sink disposed over at least the thermoelectric element. The thermoelectric element may be configured to transfer heat from the first integrated device die to the heat sink. The thermoelectric element directly may be bonded to the first integrated device die without an adhesive.