A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

An embodiment is a method including forming a first interconnect structure over a first substrate, forming a redistribution via over the first interconnect structure, the redistribution via being electrically coupled to at least one of the metallization patterns of the first interconnect structure, forming a redistribution pad over the redistribution via, the redistribution pad being electrically coupled to the redistribution via, forming a first dielectric layer over the redistribution pad, and forming a second dielectric layer over the first dielectric layer. The method also includes patterning the first and second dielectric layers, forming a bond via over the redistribution pad and in the first dielectric layer, the bonding via being electrically coupled to the redistribution pad, the bond via overlapping the redistribution via, and forming a first bond pad over the bonding via and in the second dielectric layer, the first bond pad being electrically coupled to the bond via.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over an active side of a semiconductor die. A die pad of the semiconductor die is connected to an interconnect segment of the RDL by way of a bond wire. An encapsulating layer is formed over the active side of the semiconductor die such that exposed portions of the die pad and the bond wire are embedded in the encapsulating layer.

Example embodiments are directed to a semiconductor device including a substrate, a substrate pad placed on the substrate, a substrate insulation layer configured to surround at least a portion of the substrate pad, a passivation layer placed on the substrate insulation layer and a bump pad placed on the passivation layer, electrically connected to the substrate pad and including solder bumps. The bump pad includes a connector recessed toward the substrate, and the connector, when viewed in a first direction perpendicular to a surface of the substrate, includes a shape, in order to reduce or lower a defect occurring in solder bumps when a degree of expansion and contraction varies due to differences in the coefficient of thermal expansion (CTE).

A die includes a substrate, a conductive pad, a connector a protection layer, and a passivation layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector comprises a seed layer and a conductive post on the seed layer. The protection layer laterally covers the connector. The passivation layer is disposed between the protection layer and the conductive pad. The conductive post is separated from the passivation layer and the protection layer by the seed layer.

A layered body contains: a first resin layer; a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which the first resin layer comprises a storage portion, and the first conductive layer is disposed within the storage portion of the first resin layer. A conductive layered body contains: a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which an adhesive layer is provided between the first conductive layer and the insulating layer, and between the insulating layer and the second conductive layer, respectively.

A layered body contains: a first resin layer; a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which the first resin layer comprises a storage portion, and the first conductive layer is disposed within the storage portion of the first resin layer. A conductive layered body contains: a first conductive layer; an insulating layer; and a second conductive layer; in this order, in which an adhesive layer is provided between the first conductive layer and the insulating layer, and between the insulating layer and the second conductive layer, respectively.

A semiconductor device includes a first conductive portion, a second conductive portion, a first semiconductor element, a second semiconductor element, two first terminals, a second terminal, a third terminal, a first conductive member, a second conductive member, a plurality of first control terminals, a plurality of second control terminals, and a sealing resin. In a first direction orthogonal to the thickness direction, the first conductive portion and the second conductive portion are spaced apart from each other. The second terminal and the second conductive member form a conduction path located outside the plurality of first control terminals in a second direction orthogonal to the thickness direction and the first direction.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.