Provided is a semiconductor device including a substrate, a channel layer on the substrate and having a first material, a barrier layer located on the channel layer and including a second material having an energy band gap different from that of the first material, a gate electrode located on the barrier layer and extending in a first direction, a gate semiconductor layer located between the barrier layer and the gate electrode, a source electrode connected to the channel layer and spaced apart from the gate electrode in a second direction perpendicular to the first direction, a drain electrode connected to the channel layer and spaced apart from the gate electrode in the second direction in the second direction, and a crack propagation prevention structure located on a side of the source electrode and connected to the source electrode, and penetrating through the channel layer and the barrier layer into the substrate.

An implantable integrated circuit medical device platform having integral and monolithic circuit traces. The platform allows for implanting the device into a mammalian body single and multi-functional interface devices for sensing, monitoring stimulating and/or modulating physiological conditions within the body. Microelectronic circuitry may be integrated onto the platform or may be joined as modular components to the platform.

A power semiconductor device includes a semiconductor structure comprising an active region, an encapsulation material on the semiconductor structure, and a plurality of adhesion features in or on the semiconductor structure along an interface with the encapsulation material. The interface is laterally between the active region and at least one edge of the semiconductor structure. Related devices and fabrication methods are also discussed.

A semiconductor package according to some example embodiments may include a chip base including a main chip region and an edge region around the main chip region, a device layer on the chip base, a wiring layer on the device layer, an upper insulating stack on the wiring layer, and a trench on the edge region, the trench recessed from the upper insulating stack to the device layer, and an inner surface of the trench exposed to an outside of the semiconductor chip.

A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.

In one example, an electronic device comprises a substrate comprising a first side and a second side opposite the first side, wherein the substrate comprises a first groove at the second side of the substrate, a first electronic component over the first side of the substrate, and a resin in the first groove. The substrate comprises a floating pad at the first side of the substrate, a second groove at the first side of the substrate, and a third groove at the first side of the substrate, wherein the floating pad is between the second groove and the third groove. Other examples and related methods are also disclosed herein.

A semiconductor device with a multi-tier construction includes a first tier having a first die, a second die spaced apart from the first die in a first direction and a fill material therebetween. A second tier overlays the first tier, and includes a bridge die partially overlaying the fill material and the first and second dies. The bridge die provides an electrical interconnection between the first and second dies in the first tier. The device also has a first protective structure aligned with a first interface between an end of the first die and the fill material that includes a first part formed on a first side of the first die at the end of the first die; and a second part formed on a first side of the bridge die. The first and second parts are aligned and form the first protective structure, mitigating cracking near the bridge die.

A semiconductor package includes a first die and a second die disposed side-by-side, an encapsulant laterally covering the first die and the second die, and an interconnect structure underlying the encapsulant. Each of the first die and the second die includes a front side and a back side opposite to each other. The second die further includes an optical interface at the back side, and a top surface of the back side of the second die and the optical interface are exposed by the encapsulant. The interconnect structure is connected to the front sides of the first and second dies, and the second die is electrically coupled to the first die through the interconnect structure.

A microelectronic circuit package may include one or more operative channels, each of the one or more operative channels containing a reactive material, and a seal covering at least a portion of the one or more operative channels. At least one of the one or more operative channels has a maximum width of less than about 100 microns. The seal is non-reactive with the reactive material. Also disclosed are methods of manufacturing a microelectronic circuit package comprising at least one operative channel containing a reactive material.

A semiconductor device comprising: an upper surface; a lower surface opposite to the upper surface; a first side surface; a second side surface contiguous with the upper surface and having irregularities; a step surface connecting the first side surface and the second side surface and facing upward; and a protective film covering at least a part of the upper surface, the entire second side surface, and at least a part of the step surface.